Can anyone confirm the frequency the C64 CIA 16bit timers tick per second ?
In the C64, the 6526/8521 CIA chips run at the phase 2 system clock rate, which is set at either 0.985248MHz (PAL) or 1.022727Mhz (NTSC).
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I working with EFM microcontroller (Silicon Labs)
I need to make a beep every x seconds, when the device in EM3 mode.
I tried so many ways without success.
Please try to help me with code example (I'm HW man, not a SW haha)
Thanks,
Gal.
Refer to page 8 on the datasheet (thanks to #user694733)
EM3 mode description:
still full CPU and RAM retention, as well as Power-on Reset, Pin reset and Brown-out Detection, with a consumption of only 0.6 μA. The low-power ACMP, asynchronous external interrupt, PCNT, and I2C can wake-up the device.
So these are your options. One of these things can wake up the microcontroller. All of them are external inputs. So the microcontroller cannot wake itself up in this mode. This makes sense because all clocks are stopped.
If you had an outside clock connected to the PCNT you could use that to wake it up.
If you want the microcontroller to wake itself up, then you need EM2 mode or less:
In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz
oscillator running, selected low energy peripherals (LCD, RTC, LETIMER,
PCNT, LEUART, I2C, WDOG and ACMP) are still available
In EM2 mode the microcontroller may wake itself up using the RTC (real-time clock), LETIMER (low-energy timer), WDOG (watchdog timer) or PCNT (pulse counter, which can be set to count pulses of the 32.768kHz clock).
The datasheet recommends using the Real-Time Clock or Low Energy Timer (RTC or LETIMER) modules.
... however, if we pay attention, we see the datasheet mentions something called the ULFRCO, Ultra-Low-Frequency RC Oscillator, which runs at approximately 1000 Hz. By searching for the keyword ULFRCO, we see that it does still run in EM3 mode, and it can be used as input for the WDOG. On page 89 we see this listed as a feature of EM3 mode.
So, you may configure the WDOG to reset the system after a few seconds. When the microcontroller resets due to watchdog timeout, it wakes up. You should not be afraid of using a system reset. The RMU_RSTCAUSE allows you to see that the system was reset because of the watchdog timer (not because it was first turned on or the reset pin was used). Memory contents are probably still there, but all peripherals are reset. As long as you can deal with peripherals being reset, you can probably make this work. You might even be able to use a little bit of assembly programming to jump back to exactly the point where the program left off.
I am trying to understand how timer on the internal clock works.
I've attached my CubeMX config below.
For now, I have set the main clock to 480 MHz which is the maximum for this STM32H743ZI chip.
I am using TIM 2 so I am looking at APB1.
there from the clock tree I see that it is currently so to 240 MHz for Timer Clocks, and 120 MHz for Peripheral Clocks.
My first question is that why is it using the 120MHz where it clearly says "240 MHz" for "timer clocks on APB1"? I have verified the frequency with an oscilloscope.
It is a long shot but according to what I read is that the maximum timer clock for this chip is 200 MHz. So 240 being greater than 200, perhaps the chip is automatically applying a /2 divider? I would think the clock configuration tree would say something, instead of allowing the "240 MHz" to be applied?
My second question:
For the sake argument, let's say that the maximum timer clock really is 200 MHz, how do I go about setting 200 MHz as clock frequency for APB1? I am sure there is no way to achieve 200 MHz without compromising on the max MCU clock and bring it down from 480 to 400 MHz perhaps?
Can I trust the automatic prescaler/multiplier adjustments that CubeMX is doing whenever I change something?
How did you checked it with the scope? It is inside the chip?
The timer clock is 240MHz, other peripheral clocks connected to the APB1 are 120MHz.
according to what I read is that the maximum timer clock for this chip
is 200 MHz.
Where did you read that? official documentation says something different
I think this question does not make too much sense
You see the values, you can check them manually if you wish, but in this case computers are usually are better than humans. Personally I did not have any problems with Cube. BTW I use it only for the clocks (I am too lazy to calculate all the prescallers by hand), but I program it bare register way.
I'm new to ARM MCUs (STM32F411), and I have been trying to find my way around the peripherals using STM's HAL library and STM32Cube.
I've already configured my board in order to use some peripherals:
Timer 2 for running an interrupt with a certain frequency
Timer 3 for running PWMs on 3 channels of it.
ADC with 4 channels, into DMA mode, for reading some analog input.
Let us suppose, now, that the PWM's whole period is 100 ms and its duty cycle is 50% (50 ms PWM on and 50 ms PWM off).
I would like to trigger an interrupt after a certain time of the PWM on level, let us say 50% of it.
Hence, I would like to run an interrupt at 25 ms in order to use the ADC for sampling it's analog inputs.
Do you have any suggestion on how could I implement such a kind of interrupt?
Thank you in advance for your help!
Since the ADC of the STM32F411 is used in Regular mode (not Injected mode) and only three channels out of four are used to generate PWM on Timer 3, the fourth channel can be used to trigger the ADC.
Hence Timer 3 is configured as follows:
CH1 used for Output Compare mode 0 (TIM3->CCMR1.OC1M = 0)
CH2, CH3, CH4 used for PWM outputs
Therefore TIM3->CCR1 is loaded to a value that gives 25% of duty, then it will generate TIM3_CH1 events that can be used to trigger ADC start-of-conversion at 25% of your TIM3 timebase.
Im using Ethernut 2.1 B and I need a C program that outputs a clock signal at the timer 1 output B, with other words on output OCIB. The frequency of the clock signal should be at 1.0 kHz.
Anyone know how this could be done?
You need to look in COM bits for your timer. For instance, for Timer0 (8-bit), the COM bits are set in the TCCR0 register. Probably the setting you'd be interested in is
TCCR0 |= (0<<COM1)|1<<COM0); // Toggle OC0 on compare match
This will toggle the OC0 (pin14) line when timer reaches the specified value.
Which timer you use depends on the precision you need: obviosely the 16-bit timers can give you more precise time resolution then the 8-bit timers.
The setting of the registers for your specific frequency (1Khz) depends on the clock speed of your chip, and which timer you are using: the timers use a pre-scaled general clock signal (see table 56 of the datasheet for possible values). This means that the prescaler settings will depend on your clock speed, and how high you want to count. For most precision you will want to count as high as possible, which means the lowest possible prescaler setting compatible with your timer's maximum value.
As far as where to start, generally, reading the datasheet is a good place, but googling "AVR timer" can also be very helpful.
It seems to be based on the Atmel ATmega 128, so read that CPU's data sheet to figure out how to program the timer hardware.
Not sure if this microcontroller supports directly driving an output from a timer, if it doesn't you're going to have to do it in software from the interrupt service routine.
I am trying to add the 'independent watchdog' functionality to a project. It works fine but I am putting the chip to sleep for extended periods to conserve the battery and the watchdog still wakes everything up and forces a reset. Is there any way to disable the low speed internal oscillator? I haven't been able to find any info on that.
Thanks
I am using the ST Micro stm32f103v8 cortex M3. It turns out with this device it is impossible to disable the independent watchdog or disable the LSI oscillator once the watchdog has been enabled. Since the max watchdog time is about 37 seconds the current solution seems to be to wakeup every 25 seconds (to account for oscillator temperature speed differences) and reload the counter before going back to sleep. I am going to do a power analysis on this in the next couple weeks and see if it makes sense.
You could use the System window watchdog (WWDG) instead of the Independent watchdog (IWDG). The WWDG will be halted when you go into sleep/stop since you stop the APB clock (PCLK)