Platform - ARM9
I have a third party device connected via I2C to the ARM9. My problem is the I2C read/write is getting in a twist. It appears the IRQ line is asserted but never de-asserted when there is data to read. The read fails as the third-party device NACKs the address packet. So any subsequent write fails.
I am wondering if my interrupt handling in ok. In the ISR that services the IRQ, I disable interrupts, unregister the interrupt handler and then signal to the task to go read from the I2C bus. Finally, I re-enable the interrupts.
When the task services the signal posted above, I attempt to read data from the I2C bus but this fails. Finally, I always reregister the ISR after ever read attempt. There is no interrupt disabling/enabling that takes place during handling of the read signal.
My question is do I need to disable interrupts when reading/writing to the I2C bus?
Programming language of choice is c using propriety RTOS.
An important thing is whether your RTOS/system is ready to support nested exceptions. Unless there is a good reason to do so, things are simpler if you avoid nested exceptions and disable all interrupts when entering an ISR and re-enabling when leaving.
If you want to allow other higher-priority interrupts to occur while you are serving the I2C interrupt, then disable only the I2C interrupt. It is rather unusual to unregister an interrupt handler when entering an ISR. This may lead to unexpected behaviour, when there is no registered handler, the interrupt itself is enabled and an interrupt occurs. So instead of unregistering the handler, simple disable the I2C interrupt (Perhaps you are already doing so, but as I see it, registering a handler and enabling an interrupt are two different things).
A good strategy to solve your problem will be to try to communicate with the device without interrupts. Try to read/write from it in a serial fashion, doesn't matter if everything blocks - it is just testing. This is much easier to debug and after you are successful you can move to the interrupts version.
Most interrupts need to be acknowledged or cleared. You mention enabling/disabling, registering/unregistering and handling the interrupt. Just check that the interrupt is being acknowledged and/or cleared/reset. Often this involves writing the interrupt number or bit back to the interrupt pending register. Check the specific ARM manual or your RTOS manual.
Whether you need to enable/disable interrupts for your target platform is dependant on your specific hardware/RTOS implementation. Unfortunately, every ARM microcontroller vendor (STMicro, Freescale, Oki, etc) has the ability implement their I2C hardware differently and may have different requirements in how to clear the IRQ.
I'd recommend you find a copy of the hardware datasheet (and/or post the specific hardware part-number here so we can help pour over the vendor documentation, with you).
Related
Is there any Hardware emulator which can generate hardware interrupt on Linux. I am looking to write device drivers that could process hardware interrupts, read or write into hardware memory, deferred work, top and bottom halves processing, etc. Basically, looking to learn complete device driver end to end. But what hurdle is - how to simulate hardware. Do I really need some hardware that could generate an interrupt. I went through book LDD3, but there they are using skull - a chunk of kernel space memory emulating as a hardware, but this cannot generate an interrupt, or it can? pls, throw some light.
The skull driver of LDD3 doesn't generate interrupts, because there's no actual hardware to generate them.
Device driver interrupts are a mechanism that allows the cpu to begin attending some other task because the action being performed will be handled by an asynchronous interrupt.
For example, a floppy disk drive interrupt's the cpu as each byte of a disk transfer is readin if no dma is in use. If DMA is being used, the disk will transfer directly to ram the bytes of the transfer until a full block (or a set of them) is actually transferred. Then some hardware interrupt will come in.
A serial interface interrupts your computer in a programmed basis. When a single character arrives, when a specific character arrives (let's say a \r char).
LDDP shows you how linux device drivers work..... but as the book cannot assume you have any concrete device, it is not capable of selecting a proper hardware to serve as usable (strange, as normally every pc has a parallel port or a serial port) I think LDDP3 has some driver using the parallel port, but you must continue reading the book before you start with interrupting hardware.
Asynchronous interrupts must be programmed into the device (the device must know that it has to generate an interrupt at the end of the transfer) so they have to be activated. For the interrupt to be properly catched, an interrupt handler must be installed before the first interrupt happens, or you'll get in an state in which no interrupt comes ever, because it arrived and was lost. And finally, interrupts have to be acknowledged. Once you have stored the data comming from the device, they have to be reactivated, so another interrupt can happen again. You need to learn that you have to protect your processes from accessing the data structures shared with an interrupt handler and how to do this. And all of this is explained in the book.... but you must read it, and don't stop in the skull driver which is the first driver developed in the book.
By the way, the kill(2) and sigaction(2) system calls of user mode are a very close approach into the world of hardware interrupts, because they are asynchronous, you can block them to occur, before entering a critical zone, and you can simulate them by kill(2)ing your process externally from another program. You will not see the difference, but instead of having a full system crash, you only get a hung process to kill.
I was learning about interrupts and came here to see if someone can help me!
A) I understand that the interrupt is the electrical signal sent by some external hardware to the processor, via one of the input ports.
B) I understand that in some MCU's more than one input port are "attached" to only one interrupt.
Can exist an useful input port in a MCU that is not linked to any interrupt at all?
A) I understand that the interrupt is the electrical signal sent by
some external hardware to the processor, via one of the input ports.
That is surely one class of interrupt, sure, as long as you understand that 'external hardware to the processor' can mean 'internal to the controller chip' - many MCU have extensive integrated peripherals.
B) I understand that in some MCU's more than one input port are
"attached" to only one interrupt.
Yes - that is not uncommon. The intrrupt-handler then has to poll the port to find out which GPIO/whatever pin generated the interrupt.
Can exist an useful input port in a MCU that is not linked to any
interrupt at all?
Sure, especially on 'trivial' controllers that do not require high-performace IO and have no RTOS.
Even higher-performance MCU apps may poll for sundry reasons. One common example is reading keypads. The input rate is very low and the mechanical switches need to be debounced. Fastening every KB read line to an interrupt line may cause unwanted multiple interrupts. Such iputs are better polled, though even then, a timer interrupt often handles the polling.
The answer is probably "yes," but it depends on the microcontroller architecture. There's no guarantee that one vendor's MCU will behave the same as any other (with respect to interrupts, ports, or anything else). If you're tasked with learning a particular MCU, then learn it, live it.
You house may have only one doorbell button. But pretty much anyone can use it for whatever reason. UPS there is a package. neighbor kid to play with your kid. someone trying to sell something and so on. A processor is no different. To reduce latency newer designs may have multiple interrupt signals on the core so that the handler doesnt have to do as much if any work to figure out who caused the interrupt. Kind of like having ringtones for every person on your phone, so you can tell without looking who is calling. Vs. one ringtone for everyone and you have to look.
Do not confuse external gpio ports on the chip with interrupt lines, they are not. they are general purpose I/O. they might have a way to be used as interrupts or not, depends on the design of the chip. Again as with the doorbell on your house, there are many things, technically all of them are within the chip (microcontroller), that create interrupts. Because software has to setup handlers before it can...handle...interrupts, all sources of interrupts are disabled at first, and only the ones software enabled have the ability to actually reach the core and cause an interrupt. Logic in the chip. so you may have an interrupt signal tied to the uart receiver and you might enable that. You might have one for the tx buffer, when it is empty interrupt. but you have to enable those before the processor can get an interrupt. there is a small section of logic that does fire an interrupt every time one of those events occurs, but that signal is gated and cannot reach the core, blocked by logic you control.
You can have timers in the mcu, that interrupt you when they roll over or count to zero. But you have to not only setup the timer to do that with software, you also have to enable the interrupt from making it across the chip from the timer to the processor core.
And yes sometimes the gpio peripheral has a way to interrupt the processor as well. as with everything else you have to with software setup the peripheral and define what interrupts you want and you have to enable them across the chip.
There are more different ways of doing this than there are companies making chips as they dont always do it the same way across their product lines. But generally at a minimum there is an interrupt enable on the peripheral end, one or many depending on the peripheral and features, that you have to enable in order for that signal to leave that peripheral on its way to the core. And there is often an interrupt controller peripheral or something built into the core or near it that takes all the dozens or hundreds of individual interrupt connections in the chip and prioritizes them and orrs them into the one or few interrupt lines into the core. you generally have to also enable the corresponding interrupt that matches the signal coming out of your peripheral to reach the processor core. And then there is sometimes an interrupt enable in the core itself so that even if you have the peripheral enabled, the interrupt controller enabled for that one peripherals interrupt, you still cannot interrupt the processor unless the interrupt enable in the processor core is enabled. That is the simple case, it can get more complicated if there are more layers of interrupt controllers along the way. Well the simple case is when you have something like a cortex-m with dozens or hundreds of individual interrupt signals, still have interrupt enables on both ends and in the core, just easier to manage as you have dozens to hundreds of interrupt handlers instead of one mega handler for everything.
So dont confuse the pins on the chip as being interrupts, on older dedicated processors, like the 8088/86, sure that was the one interrupt pin. But general purpose I/O sometimes called GPIO sometimes called ports, are just a peripheral, they are just pins you can make go high or low, they are not there to be interrupts although there may be a feature in that peripheral for that (or maybe there isnt). And again interrupt signals go through logic gates and have to be enabled, by software, at a minimum on both ends of that signal, at the peripheral and at the interrupt controller.
I was wondering, because it seems to be different (for example WFI and WFE are separate instructions), but I can't exactly pinpoint the thing.
After a few years, I see this question is popular, and in the mean time I understood the answer by experience.
Events are implemented as lines entering the MCU ARM core, alongside the memory bus (actually the core can generate events too, the lines are one way and point to point dedicated, this is not a bus), so that peripherals or other cores can raise those lines to tell stuff in real time to the core outside any memory bus management or instruction execution, even if there is no bus arbitrer in the MCU (I guess they are clocked at bus frequency, tho).
Those events are then handled by the core, and one way to make the event enter the program world it by raising an interrupt (more exactly, plugging the line to the NVIC, that can interpret it as an interrupt), by flipping a bit in one of the core registers, by re-starting the core clock or they can be plugged to a DMA peripheral to start or stop a transfert. There is a whole logic part dedicated to event management in the core, to mask them, use them as sources for exception or as source of DMA actions.
The list of events is decided by the MCU implementers, they can decide to use an NVIC, a DMA, or connect them to PLD logic (some cypress MCU can trigger a DMA or interrupt from the PLD part).
The absolute most common way to handle an event is to ignore it, and the second most common is to send an exception to execute some code.
Both instructions are meant for power management/saving. While WFI is supposed to halt the core till an interrupt or exception occurs, WFE will also wait for an "event", which can be send by the SEV instruction.
It is implementation defined to which level the instructions are implemented, they might be just NOPs. So for example you can not trust that an interrupt or "event" really occurred when WFE returns.
I am using mini2440 arm board, and GPIO to control the hardware connected with the GPIO. I am using BSP that ships with the cd of the board. I have only enabled functionality which I will need for running the hardware.
I have disabled audio, Ethernet and unnecessary stuff in kernel, so that it don;t cause interrupt hence CPU attention. But the problem is sometimes some interrupt occur on the GPIO and hardware do malfunction. I know I can see all interrupt via cat /proc/interrupt, but how should i know which interrupt occur on GPIO from which device?
I am running my application with highest nice priority (-20), but still sometime external interrupt occur.
When i send data on GPIO, only TimerTick of s3c2440 do interrupt, but that's fine, it is require, but not other. Please tell me how to find which interrupt occur (I know I can check it via cat /proc/interrupt) and how to disable (Disable interrupt on ethernet via ifconfig eth0 down) interrupt from kernel? Need some expert solution, I have tried the solution getting help from people but need some expert solution.
Disabling devices in the kernel has no real efect on interrupts (generated by the hardware), it just affects how software handles them. If the device isn't present, no interrupts get generated. And Linux was written by absolute performance freaks, barring misbehaving hardware the interrupt handling is nearly as good/fast as it could be.
What exactly are you trying to do? Are you sure you aren't trying to get performance that your machine just can't deliver?
What is the difference between a signal, a software interrupt and a hardware interrupt?
Please tell me with one example??
In the C language, signals mean a form of internal program communication found in signal.h. You could perhaps compare them with "events" or "excpetions" in other languages or in the OS. It was an attempt to give language support to such OS functionality. http://en.wikipedia.org/wiki/Signal.h
Software interrupt refers to specific interrupts in the CPU that were caused by the software going wrong on a low, fundamental level, i.e. executing an unknown OP-code or attempting to access unused memory areas. The software interrupt is called by the CPU itself and not by the OS or application.
Hardware interrupts are every other kind of interrupt that isn't a software one. They are called by the CPU itself. Their nature is application- and hardware specific.
From wikipedia:
In computing, an interrupt is an
asynchronous signal indicating the
need for attention or a synchronous
event in software indicating the need
for a change in execution. A hardware
interrupt causes the processor to save
its state of execution and begin
execution of an interrupt handler.
Software interrupts are usually
implemented as instructions in the
instruction set, which cause a context
switch to an interrupt handler similar
to a hardware interrupt.