C Makefile with two executables and a common directory [closed] - c

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I need to make a makefile which compiles two executables, cassini and saturnd
I've been having a ton of problems with this makefile I'm using. Sometimes it compiles, sometimes not.
Makefile
CC = gcc
CFLAGS = -std=c11 -Wall -Wextra -Wpedantic -Wstrict-aliasing -I include
SRCCASSINI = $(wildcard src/cassini/*.c)
SRCSATURND = $(wildcard src/saturnd/*.c)
SRCCOMMON = $(wildcard src/common/*.c)
OBJCASSINI = $(SRCCASSINI:.c=.o)
OBJSATURND = $(SRCSATURND:.c=.o)
OBJCOMMON = $(SRCCOMMON:.c=.o)
EXEC = cassini saturnd
all: objs $(EXEC)
objs: $(OBJCOMMON)
cassini : $(OBJCASSINI)
$(CC) -o $# $(OBJCASSINI) $(OBJCOMMON)
saturnd : $(OBJSATURND) objs
$(CC) -o $# $(OBJSATURND) $(OBJCOMMON)
%.o : %.c
$(CC) -o $# -c $< $(CFLAGS)
clean :
rm -f src/*/*.o $(EXEC)
distclean :
rm -f src/*/*/.o $(EXEC)
Project structure
Include dir:
include contains the .h files of all c files and more.
SRC dir:
SRC contains 3 directories:
cassini* contains all source files that should be compiled only with the cassini executable
saturnd contains all source files that should be compiled only with the saturnd executable
common contains all source files that should be compiled with both cassini and saturnd
Screenshot : https://prnt.sc/26brtpq
make will fill my screen with verbose output. Sometimes it compiles, sometimes not. For some reason.

Without knowing what kinds of problems, specifically, you see it's hard to say for sure. But, one issue is your cassini target doesn't list any of the common objects as prerequisites. That means when cassini is linked it might be using older, not-recompiled versions of the object files (or they might be missing altogether).
You should change your link targets to this:
cassini : $(OBJCASSINI) $(OBJCOMMON)
$(CC) -o $# $^
saturnd : $(OBJSATURND) $(OBJCOMMON)
$(CC) -o $# $^
and see if that works better. If that doesn't help then your makefile looks correct so it must be something you haven't shown us here, and the only way to help with that is to see exactly how you invoke make and some explicit errors; as mentioned above please don't attach, or link to, screenshots: instead edit your question and cut and paste the text, with formatting.

The trick is not to use a makefile. I've been programming for years and still can't reliably make one of those do what I want.
Instead, you use cmake. It has an easy syntax which you can mostly copy-paste from one project to another and generates makefiles which reliably Do The Right Thing™.
To use cmake, you make a file called CMakeLists.txt in the parent directory of src. Put this in the file:
cmake_minimum_required (VERSION 3.9)
project(cassini_saturn LANGUAGES C)
SET(common_files
src/common/g.c
src/common/h.c
src/common/i.c
)
add_executable(cassini
src/cassini/a.c
src/cassini/b.c
src/cassini/c.c
${common_files}
)
target_compile_features(cassini PRIVATE cxx_std_11)
target_compile_options(cassini PRIVATE -Wall -Wextra -Wpedantic -Wstrict-aliasing)
target_include_directories(cassini PRIVATE include)
add_executable(saturnd
src/saturnd/d.c
src/saturnd/e.c
src/saturnd/f.c
${common_files}
)
target_compile_features(saturnd PRIVATE cxx_std_11)
target_compile_options(saturnd PRIVATE -Wall -Wextra -Wpedantic -Wstrict-aliasing)
target_include_directories(saturnd PRIVATE include)
Edit the obvious places so that the files your project uses are each listed individually. It is a best practice to list all the files, rather than relying on wildcards and globs, though if you want to not follow best practices you can use, eg:
file(GLOB SRC_FILES src/common/*.c)
Now that your CMakeLists.txt file is set up, it's time to use it. To do so, you'll run the following:
mkdir build/
cd build/
cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo ..
make
You make a directory called build (it could be named anything) to contain all the byproducts of building and compiling your project. That way, you can just rm -rf build/ to get a clean slate. This is called an out-of-source build and it is a best practice.
The line
cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo ..
generates a makefile for your project that, when run, will build your project with optimizations and debugging info. Other options are Release (all optimizations, no debugging info) and Debug (no optimizations, debugging info).
The final line, make, runs the generated makefile and builds the executables inside the build directory.

Related

How to create a static library for the files located in multiple directories with out specifying files names in the Makefile [duplicate]

This question already has answers here:
Makefile issue: smart way to scan directory tree for .c files
(4 answers)
Closed last year.
I need to create a static library using source files in different directories. I am able to create static library by specifying each and every source file in the Makefile. It increased more content in the Makefile.
Let me explain what I did with an example:
#Specifying the each and every source files to FILES is more complex to me. Trying to find out alternative to this problem
Files = Source1\A.c Source\B.c Source2\C.c Source3\D.c ........... Sorce3/Z.c
$(OUT_FILE_NAME): $(patsubst %.c,%.o,$(wildcard $(FILES)))
ar -r -o $# $^
#Compiling every *.c to *.o
%.o: %.c dirmake
arm-none-eabi-gcc -c -o $# $<
I'm trying to explore alternative way to specifying all source files in the Makefile. This will help us to not modify this Makefile again if any new source file added. Is it possible to do that?
I tried to search for this problem and many sources explain how to create static library but I don't see any alternative solution for this problem.
Without knowing the details of your development environment I would try these minimal changes first. Using the wildcard-function for the source directories will enable you to add more sources without having to edit the Makefile every time. Just keep the directories clean of any unused c-files to avoid including stuff in your library that you don't want.
I have also made the Files variable simply expanded (evaluated once) by using := for assignment. I also simplified the prerequisite of the first rule and fixed the case of the variable-name.
Files := $(wildcard Source1/*.c) $(Source2/*.c) $(Source3/*.c)
$(OUT_FILE_NAME): $(patsubst %.c,%.o,$(Files))
ar -r -o $# $^
#Compiling every *.c to *.o
%.o: %.c dirmake
arm-none-eabi-gcc -c -o $# $<

searching solution for creating generic makefile for compilation of multiple programs

Till now, I was using the following makefile that I have generated somehow for my school projects:
my makefile
But now I have a different situation: I am supposed to compile 4 programs for one project, while part of the code is supposed to be compiled as .so, for use for the 4 programs.
like described here:
1 - all the parts that are supposed to be compiled together as one .so file, using for example:
gcc -shared -fPIC src/file1.c src/file2.c src/file3.c -o libutils.so
3,4,5 should be compiled and linked together with this .so file, using for example:
gcc src/file4.c -L'pwd' lutils -o file4.out
the same way for all the 3 projects, and one more simple compilation of project 2.
I wandered across the net, google, your site, etc.
tried to find a solution for this situation,
without any luck.
already seen solutions like this one:
solution example
where you supply makefile with the details of the entire project structure.
I thought about dividing all the files into 4 folders, below the main folder, and creating a loop inside makefile that will compile each program in each cycle, with "if" statements to make a different compilation, according to the index. but I had no luck, it seems very complicated (maybe someone can show me a solution like that one...).
I am wondering if there is a way of making this whole compilation process generic and automatic like the current file (maybe little less),
if there is a way, I would like to study and discover it.
thank you in advance!!!
Arie
Since you have a nicely drawn tree of dependencies, you "just" need to translate this into a Makefile.
You might like to start with this:
.PHONY: all
all: reloader.exe block_finder.exe formatter.exe printdb.exe
MODULES = reloader block_finder formatter printdb linked_list bitcoin file_handler
SRCS = $(MODULES:%=%.c)
reloader.exe block_finder.exe formatter.exe printdb.exe: libbitcoin_manager.so
reloader.exe: reloader.o
block_finder.exe: block_finder.o
formatter.exe: formatter.o
printdb.exe: printdb.o
libbitcoin_manager.so: linked_list.o bitcoin.o file_handler.o
gcc -shared -fPIC $^ -o $#
%.exe: %.o
gcc $< -L. -lbitcoin_manager -o $#
%.o: %.c
gcc -c $< -o $#
%.d: %.c
gcc -MM -MT $# -MT $*.o -MF $# $<
include $(SRCS:%.c=%.d)
Because you don't have a loop in the diagram, you don't need a loop in the Makefile. Instead you put all dependent files on the left of a colon and the file they depend on on the right.
You might like to collect more "objects" in variables, for example the programs to build, the modules in the library, and so on.
I have also used a common pattern to generate the dependencies from the header files. The way shown is just one way to do it. It uses files with a ".d" extension, for "dependency." GCC has options to build these files, it scans the source and collects all included headers even if "stacked."
For example, "bitcoin.d" looks like this:
bitcoin.d bitcoin.o: bitcoin.c bitcoin.h linked_list.h definitions.h \
file_handler.h
The re-generate the dependency file on changes in the sources it is also a target, not only the object file.
EDIT:
First, using directories makes Makefiles more difficult. I don't like such structures not only for that reason, but also because they separate header files and implementation files that clearly belong to each other.
Anyway, here is an enhanced Makefile:
.PHONY: all
SRCDIR = src
INCDIR = include
BLDDIR = build
APPS = reloader block_finder formatter printdb
MODULES = reloader block_finder formatter printdb linked_list bitcoin file_handler
LIBNAME = bitcoin_manager
LIBMODULES = linked_list bitcoin file_handler
VPATH = $(SRCDIR)
SRCS = $(MODULES:%=%.c)
LIB = $(LIBNAME:%=lib%.so)
#win LIB = $(LIBNAME:%=%.lib)
EXES = $(APPS:%=%.exe)
all: $(BLDDIR) $(EXES)
$(BLDDIR):
mkdir $#
$(LIB): $(LIBMODULES:%=$(BLDDIR)/%.o)
gcc -shared -fPIC $^ -o $#
$(EXES): $(LIB)
$(EXES): %.exe: $(BLDDIR)/%.o
gcc $< -L. -l$(LIBNAME) -o $#
$(BLDDIR)/%.o: %.c
gcc -I$(INCDIR) -c $< -o $#
$(SRCDIR)/%.d: %.c
gcc -I$(INCDIR) -MM -MT $# -MT $(BLDDIR)/$*.o -MF $# $<
include $(SRCS:%.c=$(SRCDIR)/%.d)
It uses a lot more variables to simplify renaming and managing a growing library and application.
One important issue is the use of VPATH. This makes make search for sources in the list of paths assigned to it. Make sure you understand it thoroughly, search for articles and documentation. It is easy to use it wrong.
The pattern $(EXES): %.exe: $(BLDDIR)/%.o is a nice one. It consists of three parts, first a list of targets, second a generic pattern with a single target and its source. Here is means that for all executables each of them is built from its object file.
Now to your questions:
Is answered by the new proposal. I didn't add the directory but use VPATH.
Make stopped not because the exe-from-o pattern was wrong, but because it didn't find a way to build the object file needed. This is solved by the new proposal, too. To find out what happens if you delete these 4 recipes in the old proposal: you can experiment, so do it!
The dot is, like user3629249 tried to say, the present working directory. You had it in your Makefile with 'pwd' and I replaced it. This is not special to make, it is common in all major operating systems, including Windows. You might know .. which designates the parent directory.
When make starts it reads the Makefile or any given file. If this file contains include directives the files listed are checked if they need to be rebuild. make does this even if you call it with -n! After (re-)building all files to be included they are included finally. Now make has all recipes and continues with its "normal" work.

How to make cc look into /usr/local/include for header files

I encountered this problem while installing some python modules in which had dependencies on their own C libraries. The problem is, cc is not looking into /usr/local/include at all for header files. I made it work for one of those (thinking it was a problem of the modules) by adding /usr/local/include as one of the external include directories.
Then, to test, I wrote a simple hello.c file and added #include "fftw3.h" / #include <fftw3.h> and it failed to compile if I didn't explicitly add -I/usr/local/include.
I added a line in my ~/.bash_profile to export the include the directory path to $PATH; didn't work either.
So, my question is, how do I make cc look for header files in /usr/local/include (or, for that matter, in any custom directory) always without passing -I flag?
FYI: I'm using macbook pro running OSX 10.11
If you are using GCC then you have three environment variables you can use:
CPATH
C_INCLUDE_PATH
CPLUS_INCLUDE_PATH
Take a look here.
EDIT: since you specified you are working with OS X (hence Clang), they should be supported too, take a look ad the end here. It's not uncommon to have Clang mimic GCC specs just to help in compatibility.
I think you should invest some time in understanding build systems. For example gnu make. Here, look at this:
CC = gcc
CFLAGS = -Wall
DEPS = primes.h
OBJ = go.o primes.o
%.o: %.c $(DEPS)
$(CC) $(CFLAGS) -c -o $# $<
go: $(OBJ)
gcc $(CFLAGS) -o $# $^
This gives you:
The freedom to add any compiler you want. In your case that would be cc, in this example it is gcc.
use cflags to control to adjust the compiler - in the example -Wall will turn on the warnings
make your build work reproducible
prepare recipe with complex rules for compilation as your application grow
More information is available here.

Error in makefile ("no input files")

This is my absolute first time ever making a makefile, and I'm really trying to understand the process.
I'm trying to create a very simple makefile for a C++ project whose structure is as follows:
root folder
makefile
readme
src folder
...source files all here...
include folder
...header files for external libraries here...
lib folder
...external lib files all here...
bin folder
...output directory for built executable...
obj folder
...object files all here...
I followed the tutorial here.
Here's my makefile:
IDIR=include .
CC=g++
CFLAGS=-I$(IDIR)
ODIR=bin/obj
LDIR=lib
LIBS=none
SRC=src
_DEPS=hello.h
DEPS=$(patsubst %,$(IDIR)/,%(_DEPS))
_OBJ=file1.o file2.o
OBJ=$(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: $(SRC)/%.cpp $(DEPS)
$(CC) -c -o $# $< $(CFLAGS) # $(LIBS)
test_proj: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
.PHONY: clean
clean:
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~
When I run make on this, I get the following error:
g++ -o .o
g++: fatal error: no input files
compilation terminated.
<builtin>: recipe for target '.o' failed
mingw32-make.exe: *** [.o] Error 1
I'm using GNU Make 3.82.90 built for i686-pc-mingw32, if that matters at all.
Can anyone point out whatever ridiculous error I'm making?
IDIR=include .
is the first problem. Replace it by:
IDIR=include
With your code CFLAGS is expanded as:
-Iinclude .
It does not make sense, I'm afraid. The second problem is:
DEPS=$(patsubst %,$(IDIR)/,%(_DEPS))
which should probably be:
DEPS=$(patsubst %,$(IDIR)/%,$(_DEPS))
and would expand as:
DEPS=include/hello.h
if you fix the first problem, else as:
DEPS=include ./hello.h
which does not make sense neither. The cumulated effect of these two errors are strange recipes (I didn't try to expand them by hand) that probably trigger a make implicit rule with wrong parameters.
IDIR=include .
CC=g++
CFLAGS=-I$(IDIR)
This is wrong. First, for C++ code, use CXX not CC and CXXFLAGS not CFLAGS. Run make -p to understand the builtin rules of your make.
Then -I$(IDIR) does not "distribute" the -I, and IDIR is never used elsewhere. So I suggest to start your Makefile with:
CXX=g++
MY_CXX_LANG_FLAGS= -std=c++11
MY_CXX_WARN_FLAGS= -Wall -Wextra
MY_CXX_INCL_FLAGS= -I. -Iinclude
MY_CXX_MACRO_FLAGS= -DMYFOO=32
### replace with -O2 for a release build below
MY_CXX_OPTIM_FLAGS= -g
CXXFLAGS= $(MY_CXX_LANG_FLAGS) $(MY_CXX_WARN_FLAGS) \
$(MY_CXX_INCL_FLAGS) $(MY_CXX_MACRO_FLAGS)
I won't improve your Makefile, but I do suggest to upgrade to GNU make version 4 if possible (and compiling make 4.1 from its source code is worthwhile in 2015) for that purpose. If possible enable GUILE scripting in it.
If you are forced to use make 3.82 debug your Makefile using remake (with -x); if you can afford a make version 4 use its --trace option
BTW, you might consider using automatic dependencies, that is generating dependencies by passing -M or -MG (etc) flags of g++, see that.
At last, a simple project for a small program (less than a hundred thousands of source lines) might just put all (a few dozens of) its files in the current directory (then the Makefile could be simpler); your proposed directory structure might be arcane for a simple project (but could worth the pain if you have millions of C++ source lines of code). I've given several simple examples of Makefile, e.g. this & that. And GNU make source code itself has a less complex file tree that what you want.
BTW, I strongly disagree with the opinions of that answer (which I did upvote, since it is helpful). I don't feel that GNU make is senile, but I regret that, instead of using recent features available on recent versions (4.x) of make, many people prefer to use complex and arcane Makefile generators (like cmake) instead of coding a clever Makefile (for make version 4 specifically).
At last, you could use other builders, e.g. omake, icmake, ....

What is wrong with this Makefile? (header files not found)

I am modifying an old makefile in order to build a C extension for postgreSQL. The Makefile currently looks like this:
PGLIB = /usr/lib/postgresql/8.4/lib
PQINC = /usr/include/postgresql/8.4/server
CC=gcc
override CFLAGS+= $(CFLAGS_SL) -DPG_AGGREGATE
SHLIB = pg_myextlib
SRC = foo.c \
foobar.c
OBJS = foo.o \
foobar.o
all: $(OBJS)
$(CC) -shared -o $(SHLIB)$(DLSUFFIX) $(OBJS) -I$(PQINC)
cp *.so $(PGLIB)
clean:
rm -f $(SHLIB) $(OBJS)
The error I get when I run make is:
common.h:58:22: error: postgres.h: No such file or directory
Which suggests that the include path is not being added (the file exists in $PQINC).
Its a long time since I wrote the Makefile - and I haven't written many since. As an aside, I am pretty sure that 'shared' is not the gcc flag to build shared libs on Ubuntu (my current dev box) - I think the flag should be 'fPIC' - can someone confirm this?
I am runing gcc v4.4.3 on Ubuntu 10.0.4 and compiling for use with PG 8.4
Try moving the -I$(PQINC) from target all to the end of line that starts with override CFLAGS.
Placing -Isomething on the compiler line which turns object files, like those in $(OBJS), into executable will have no effect whatsoever.
You need to do it when you compile the source files.
Since your makefile doesn't explicitly show the rule for processing source files, it may well be using a default one, which is incredibly unlikely to know about PQINC.
You seem to be using the default rules to build foo.o from foo.c, which doesn't have your -I. Try adding the following rule to your Makefile:
.c.o:
$(CC) $(CFLAGS) -c $< -o $# -I$(PQINC)

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