I have a strange problem that I dont understand. Please bare with me as this is a difficult problem to deconstruct. I will thus give as much information as I can with test cases and results I have found.
The problem:
I need to set PA6 LOW and then use the DAC. When the DAC is changed in a transient manner, the pin PA6 will not return to 3V when set to HIGH.
In other words, the DAC causes the upper voltage limit of PA6 to be 0.6-0.8V.
I have confirmed this with oscilloscope.
The following piece of code is called inside a task/thread and executed at 50Hz:
if (enable == 1)
{
HAL_GPIO_WritePin(PROPULSION_ENABLE_GPIO_PORT, PROPULSION_ENABLE_GPIO_PIN, GPIO_PIN_RESET);
HAL_DAC_SetValue(&PropulsionModule_DAC, PropulsionModule_DAC_CHANNEL, DAC_ALIGN_12B_R, PropulsionData.propulsionSetPoint_12bit);
}
else
{
HAL_GPIO_WritePin(PROPULSION_ENABLE_GPIO_PORT, PROPULSION_ENABLE_GPIO_PIN, GPIO_PIN_SET);
HAL_DAC_SetValue(&PropulsionModule_DAC, PropulsionModule_DAC_CHANNEL, DAC_ALIGN_12B_R, 0);
}
Setup and environment
STM32F4 Discovery board
FreeRTOS configured with threads, queues and everything else works as expected
I have a single DAC set up on DAC_channel_2 (PA5) and a GPIO_output (PA6).
I also have these peripherals enabled, CAN bus, UART, several GPIO's, etc. Please see attached picture
Findings:
When I change the PA6 pin to PC4 (the adjacent pin) the problem goes away
When I change DAC_channel_2 to DAC_channel_1 the problem goes away
I flashed the code to two other brand new, out of the box, boards with the same errors.
Once PA6 is faulty and its high state is at 0.6V, resetting the microcontroller will reset the pin PA6 and PA6 will return to 3V in its HIGH state.
Any help would be greatly appreciated.
I found the problem. The problem is the MEMS chip on the discovery board. It is vitally important one realizes that not all pins on the discovery board are usable.
Refer to the first link below from Page 22 on which pins are available. Please note that some of the pins that are "not free" can still be used. See the application notes on each of the chips on the board in the second link.
Link 1: https://www.st.com/resource/en/user_manual/dm00039084-discovery-kit-with-stm32f407vg-mcu-stmicroelectronics.pdf
Link 2: https://ucilnica.fri.uni-lj.si/pluginfile.php/29604/mod_resource/content/1/en.DM00039084.pdf
Related
I am using Waveshare 1.54" ePaper Module. Using SPI peripheral:
CPU freq is 16Mhz
SPI Prescaler DIV by 8
MSB FIRST
CPOL=0, CPHA=1
The Display does not response but it respond with TI CC1310 properly.
The problem with SPI is after transmitting byte it does not go to ideal high state.
I have checked with logic analyser.
The SPI is initialised thus:
/****************** Initializing The SPI Peripheral ******************/
void SPI_setup(void)
{
CLK_PeripheralClockConfig(CLK_PERIPHERAL_SPI, ENABLE); //Enable SPI Peripheral Clock
//Set the MOSI, MISO and SCk at high Level.
//GPIO_ExternalPullUpConfig(GPIOC, (GPIO_Pin_TypeDef)(GPIO_PIN_6),ENABLE);
SPI_DeInit();
SPI_Init(SPI_FIRSTBIT_MSB, //Send MSB First
SPI_BAUDRATEPRESCALER_8, //Fosc/16 = 1MHz
SPI_MODE_MASTER,
SPI_CLOCKPOLARITY_LOW, //IDEAL Clock Polarity is LOW
SPI_CLOCKPHASE_2EDGE, //The first clock transition is the first data capture edge
SPI_DATADIRECTION_2LINES_FULLDUPLEX, //Only TX is Enable
SPI_NSS_SOFT,
0x00);
SPI_Cmd(ENABLE);
}
This is pretty much the same problem you had at Issue in interfacing SPI e-ink display with PIC 18F46K22 only on a different processor. Worth noting that CPHA on STM8 has the opposite sense to CPE on PIC18 which may be the cause of your error. That is to say that CPHA=1 on the STM8 has the same effect as CKE=0 on the PIC18. You really have to look at the timing diagrams for each part carefully.
From https://www.waveshare.com/wiki/1.54inch_e-Paper_Module:
Compare with the STM8 reference manual:
Clearly you need one of:
CPHA=1 / CPOL=1 (SPI_CLOCKPOLARITY_HIGH / SPI_CLOCKPHASE_2EDGE) or
CPHA=0 / CPOL=0 (SPI_CLOCKPOLARITY_LOW / SPI_CLOCKPHASE_1EDGE)
If it is the SCLK that you want to be normally-high, then you need the first option - although I fail to see why that is "ideal", the Waveshare diagram clearly indicates that either is acceptable.
I have an STM32L051 and want to drive an external DAC (SPI).
For that I would like to use the feature, mentioned in the manual, to output the internal reference voltage to the PB1 pin of the STM32.
I use the STM32Cube HAL as a basis. However the examples of using the VREF are limited to internal use for ADCs and comparators.
If I understand correctly, I can use the CFGR3 register to both enable the VREF as well as connect it to the PB1. Using the Cube drivers, I can use the HAL_SYSCFG_VREFINT_OutputSelect(SYSCFG_VREFINT_OUT_PB1) function, but to enable it, I should use either HAL_ADCEx_EnableVREFINT() or HAL_COMPEx_EnableVREFINT(). The manual information on SEL_VREF_OUT indicates that ENBUF_VREFINT_ADC must be set.
Furthermore no mention is made about the configuration of the pin itself. Should I simply declare it as a DAC Pin? An ADC Pin?
Answer
It is as simple as
if ( HALD_ADCEx_EnableVREFINT() != HAL_OK )
{
Error_Handling();
}
HAL_SYSCFG_VREFINT_OutputSelect(SYSCFG_VREFINT_OUT_PB1);
And I can see the 1.22 V on the PB1 output.
It does not require further pin (GPIO) configuration.
Complications and justification for the question (can be skipped)
I had some issues with the board from out electronic dept. and thus switched to the STM32L053-Discovery board. The above solution did not work, and I kept seeing 0V on PB1 (or PB0).
I assumed that was due to some configuration missing. However, after some further tests, I actually found that on that Discovery board, both PB1 and PB0 are reserved for a sensor. By closing the SB23 bridge, I could use PB1 back to the GPIO, and thus see the reference voltage on the pin.
I've been trying to port some of my AVR code to drive a simple SPI LCD to ARM as a learning exercise (I'm very new to ARM in general). For this I just need to use SPI in master mode.
I looked in the datasheet for my device (STM32F103C8) and found that the SPI1 pins I need, SCK and MOSI are mapped as alternative functions of PA5 and PA7, respectively, along with other peripherals (pg.29). My understanding is that in order to use the SPI function on these pins, I need to make sure that anything else mapped to the same pin is disabled. When looking at the defaults for the peripheral clock control register, however, it looks like the other features are already disabled.
I looked at the SPI section in the reference manual, including section 25.3.3 - Configuring the SPI in master mode. First I enabled the SPI1 master clock in APB2ENR and followed the steps in this section to configure SPI1 to my needs. I also changed the settings for PA5/7 to set their mode to "Alternate Function Output push-pull" (9.1.4). Finally, I enabled SPI1 by setting CR1_SPE.
From my reading, I had thought that by loading a value into the SPI1 data register after configuring SPI as above, the data would be shifted out. However, after writing the data, the TXE flag in the SPI status register never becomes set, indicating that the data I wrote into it is just sat there.
At this point, I'm assuming that there is something else I've failed to configure correctly. For example, I'm not 100% sure about what to do with the PA5/7 pins. I've tried to understand what I can from the datasheets, but I'm not getting anywhere. Is there anything else that needs to be done before it'll work?
I'm almost certain that you did not set SSM and SSI bits in SPIx->CR1 register. SPI in these chips is pretty simple, for the polled transfers you need to set SSM, SSI, SPE, MSTR, correct format (LSBFIRST, CPOL, CPHA) and proper baudrate (BR) in SPIx->CR1 and you're good to go.
I am able to put my stm32L1xDiscovery board in STOP mode with RTC running.
according to the datasheet this should draw about 1.3 µA. But my application draws 3.3 µA.
I noticed I did not put the FLASH in a low power mode during sleep. But when I did this, nothing changed.
This is what I use to go into STOP mode:
SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP);
RCC->APB1ENR |= RCC_APB1Periph_PWR;
PWR->CR |= ((uint32_t)(PWR_CR_LPSDSR|PWR_CR_ULP)); // ULP seems to have no effect on power consumption
RCC->APB1ENR &= ~RCC_APB1Periph_PWR;
FLASH->ACR |= SLEEP_PD; // seems to have no effect at all on power consumption
__WFI();
Any idea what I am missing here?
If you use discovery board your measurement may be not clear because a lot of other components consumpt some energy. It's may be protection diode, driver of 3.3V line or second MCU with ST-LINK/V2 embedded debug tool.
Where did you measure the power consumption? You should do it betwen JP1 pins 1 & 2 (Pin 2 is connected directly to Vdd). That should show the power drawn by the MCU, and of course anything that is powered by the output pins.
The trick is to properly disconnect and shut down all pins (except the wakeup source) as well as all clocks that are not needed.
Set FLASH->ACR |= SLEEP_PD
Enable all GPIO clocks
Put all unneded pins to analog mode
Disable ALL clocks except RCC_APB1ENR_PWREN and wakeup GPIOs in RCC->xxxLPENR
Then start the thing without the debugger, ST-Link (CN3) jumpers removed.
... and there might be other issues. It's hard to get it right.
I would like to implement a pulse-sensitive, aka edge-triggered, interrupt on an LPC1759 microcontroller. In the UM10360.pdf datasheet and ARM Cortex-M3 user guide, it says that interrupts can be triggered based on level- or pulse-sensitive behavior, but I am unable to find how to set this to be pulse-sensitive. Can someone please tell me where to set this?
For my particular application(interfacing the LPC1759 with an AD7794 ADC), I would like to trigger an interrupt based on the falling edge of the MISO pin. Although it is not explicitly stated that the interrupt is trigger on the MISO value, I am assuming this based on the fact that, of the four SPI signals, the MISO is the only input to the microcontroller. Please let me know if this is not correct.
See UM10360.pdf, chapter 9.5.6: "GPIO interrupt registers". You can enable rising and falling edge interrupts only on port 0 and 2 pins. The interrupt vector is the same as external interrupt 3.