Out-of-source build with yacc/bison and tab.h best practice - c

Question

I'm trying to use out-of-source builds with a project using GNU bison & flex for parsing and lexing.
Build is managed by GNU Make, and everything went well until I separated the logic from the main .y file to a new .c file.
The Makefile is adopted from this post.
The main problem is that .tab.h is generated by bison, and it is generated inside a build directory: ./build/src/parser.tab.h.
I manged to solve this problem in an ad-hoc manner, by including the .tab.h using a relative path #include "../build/src/parser.tab.h" and adding .tab.c to the dependencies for C files.
Is this considered a good practice?
Is there a way to implicitly state this in Makefile and/or including the generated .tab.h file?
Here is my C file:
#include "../build/src/parser.tab.h"
int main(int argc, char *argv[])
{
yyparse();
return 0;
}
and Makefile:
TARGET_EXEC := parser
BUILD_DIR := ./build
SRC_DIRS := ./src
SRCS := $(shell find $(SRC_DIRS) -name *.c -or -name *.y -or -name *.l)
OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
DEPS := $(OBJS:.o=.d)
INC_DIRS := $(shell find $(SRC_DIRS) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS))
CC := gcc
CFLAGS := -O0 -Wall -Wextra -Wpedantic -std=c17
CPPFLAGS := $(INC_FLAGS) -MMD -MP
LDFLAGS := -ly -ll
YACC := bison
YFLAGS := -d
LEX := flex
LFLAGS :=
$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
$(CC) $(OBJS) -o $# $(LDFLAGS)
$(BUILD_DIR)/%.c.o: %.c build/src/parser.tab.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
%.y.o: %.tab.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
%.l.o: %.yy.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
$(BUILD_DIR)/%.tab.c: %.y
mkdir -p $(dir $#)
$(YACC) $(YFLAGS) $< -o $#
$(BUILD_DIR)/%.yy.c: %.l
mkdir -p $(dir $#)
$(LEX) $(LFLAGS) -o $# $<
.PHONY: clean
clean:
rm -r $(BUILD_DIR)
-include $(DEPS)
Here are MWE lexer & parser:
%{
#include "parser.tab.h"
#include <stdio.h>
%}
ws [ \t]+
%%
{ws} { ; } // skip whitespaces
. { printf("unknown token %c\n", yytext[0]); }
%%
prgm: ;
Tree before & after:
.
├── Makefile
├── build
│   ├── parser
│   └── src
│   ├── lexer.l.d
│   ├── lexer.l.o
│   ├── lexer.yy.c
│   ├── main.c.d
│   ├── main.c.o
│   ├── parser.tab.h
│   ├── parser.y.d
│   └── parser.y.o
└── src
├── lexer.l
├── main.c
└── parser.y
.
├── Makefile
└── src
├── lexer.l
├── main.c
└── parser.y

Answer 1

First, your makefile is more confusing than it needs to be because you're using the $(BUILD_DIR) variable in some places and using a hardcoded build in other places: use the variable everywhere.
Second, no you should not include the path in your source file. That means whenever you change your makefile to move something you'll have to edit your source file as well.
Instead, just add the path to search for the header file to the compiler command line. You already have an INC_FLAGS variable that contains options to tell the compiler where to look for headers; just add a new one:
INC_FLAGS := $(addprefix -I,$(INC_DIRS)) -I$(BUILD_DIR)/src
Now you can just use #include "y.tab.h" in your source.