Already build a C program in Windows environment and make this makefile
# project name (generate executable with this name)
TARGET = Orga_L1_MATURANA
CC = gcc
# compiling flags here
CFLAGS = -Wall -I.
LINKER = gcc
# linking flags here
LFLAGS = -Wall -I. -lm
# change these to proper directories where each file should be
SRCDIR = src
OBJDIR = obj
BINDIR = bin
SOURCES := $(wildcard $(SRCDIR)/main.c)
OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
rm = rm -f
$(BINDIR)/$(TARGET): $(OBJECTS)
#$(LINKER) $(OBJECTS) $(LFLAGS) -o $#
#echo "Linking complete!"
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
#$(CC) $(CFLAGS) -c $< -o $#
#echo "Compiled "$<" successfully!"
and this tree's see of the code
.
├── bin
│ ├── lineasControl2.txt
│ ├── mipsEjemplo2.asm
│ └── Orga_L1_MATURANA
├── makefile
├── obj
│ └── main.o
├── README.md
└── src
├── 2EnlazadasCursor.c
├── cons.c
├── cons.h
├── funciones.c
├── funciones.h
├── main.c
├── operaciones.c
└── structs.h
its fine the way that im doing the makefile for both OS? Besides, i hear that ubuntu doesnt needs a makefile, is that right? I dont think so.
Related
I'm trying to use out-of-source builds with a project using GNU bison & flex for parsing and lexing.
Build is managed by GNU Make, and everything went well until I separated the logic from the main .y file to a new .c file.
The Makefile is adopted from this post.
The main problem is that .tab.h is generated by bison, and it is generated inside a build directory: ./build/src/parser.tab.h.
I manged to solve this problem in an ad-hoc manner, by including the .tab.h using a relative path #include "../build/src/parser.tab.h" and adding .tab.c to the dependencies for C files.
Is this considered a good practice?
Is there a way to implicitly state this in Makefile and/or including the generated .tab.h file?
Here is my C file:
#include "../build/src/parser.tab.h"
int main(int argc, char *argv[])
{
yyparse();
return 0;
}
and Makefile:
TARGET_EXEC := parser
BUILD_DIR := ./build
SRC_DIRS := ./src
SRCS := $(shell find $(SRC_DIRS) -name *.c -or -name *.y -or -name *.l)
OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
DEPS := $(OBJS:.o=.d)
INC_DIRS := $(shell find $(SRC_DIRS) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS))
CC := gcc
CFLAGS := -O0 -Wall -Wextra -Wpedantic -std=c17
CPPFLAGS := $(INC_FLAGS) -MMD -MP
LDFLAGS := -ly -ll
YACC := bison
YFLAGS := -d
LEX := flex
LFLAGS :=
$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
$(CC) $(OBJS) -o $# $(LDFLAGS)
$(BUILD_DIR)/%.c.o: %.c build/src/parser.tab.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
%.y.o: %.tab.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
%.l.o: %.yy.c
mkdir -p $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
$(BUILD_DIR)/%.tab.c: %.y
mkdir -p $(dir $#)
$(YACC) $(YFLAGS) $< -o $#
$(BUILD_DIR)/%.yy.c: %.l
mkdir -p $(dir $#)
$(LEX) $(LFLAGS) -o $# $<
.PHONY: clean
clean:
rm -r $(BUILD_DIR)
-include $(DEPS)
Here are MWE lexer & parser:
%{
#include "parser.tab.h"
#include <stdio.h>
%}
ws [ \t]+
%%
{ws} { ; } // skip whitespaces
. { printf("unknown token %c\n", yytext[0]); }
%%
prgm: ;
Tree before & after:
.
├── Makefile
├── build
│ ├── parser
│ └── src
│ ├── lexer.l.d
│ ├── lexer.l.o
│ ├── lexer.yy.c
│ ├── main.c.d
│ ├── main.c.o
│ ├── parser.tab.h
│ ├── parser.y.d
│ └── parser.y.o
└── src
├── lexer.l
├── main.c
└── parser.y
.
├── Makefile
└── src
├── lexer.l
├── main.c
└── parser.y
First, your makefile is more confusing than it needs to be because you're using the $(BUILD_DIR) variable in some places and using a hardcoded build in other places: use the variable everywhere.
Second, no you should not include the path in your source file. That means whenever you change your makefile to move something you'll have to edit your source file as well.
Instead, just add the path to search for the header file to the compiler command line. You already have an INC_FLAGS variable that contains options to tell the compiler where to look for headers; just add a new one:
INC_FLAGS := $(addprefix -I,$(INC_DIRS)) -I$(BUILD_DIR)/src
Now you can just use #include "y.tab.h" in your source.
I want to make a library file in lib and output file in bin directory.
But my makefile does not work.
my directory tree
~/home$ tree
.
├── bin
├── include
│ └── myhead.h
├── lib
├── libsrc
│ └── myfunc.c
└── src
├── Makefile
└── main.c
Here is my makefile
.SUFFIXES = .c .o
.c.o :
$(CC) $(INC) $(CFLAGS) $<
CC = gcc
CFLAGS = -g -c
AR = ar
OBJECTS = main.o
SRCS = main.c
LIB_TARGET = ../lib/libmyfunc.a
LIB_OBJS = ../libsrc/myfunc.o
LIB_SRCS = ../libsrc/myfunc.c
LIBS = -lmyfunc
LIB_DIR = -L../lib
$(LIB_TARGET) : $(LIB_OBJS)
$(AR) -rcv $(LIB_TARGET) $(LIB_OBJS)
INC = -I../include
TARGET = ../bin/main
$(TARGET) : $(OBJECTS)
$(CC) -o $(TARGET) $(OBJECTS) $(LIB_DIR) $(LIBS)
clean :
rm -rf $(OBJECTS) $(TARGET) core
I think it works but it does not work.
I get an ar: ../libsrc/myfunc.o: No such file or directory error
and myfunc.o file created in src directory.
I want to get files like
.
├── bin
│ └── main.out <-- new
├── include
│ └── myhead.h
├── lib
│ └── libmyfunc.a <-- new
├── libsrc
│ └── myfunc.c
│ └── myfunc.o <-- new
└── src
├── Makefile
└── main.c
Edit:
My build log
~/home/src$ make
gcc -I../include -g -c ../libsrc/myfunc.c
ar -rcv ../lib/libmyfunc.a ../libsrc/myfunc.o
ar: ../libsrc/myfunc.o: No such file or directory
make: *** [Makefile:20: ../lib/libmyfunc.a] Error 1
Tree after building
~/home$ tree
.
├── bin
├── include
│ └── myhead.h
├── lib
├── libsrc
│ └── myfunc.c
└── src
├── Makefile
├── main.c
└── myfunc.o
Can anyone help?
Note that this forum eats Tab indentation, so if you copy-paste the below Makefiles, do fix the indentation using e.g. sed -e 's|^ *|\t|' -i Makefile .
I would use
LIBSRC := libsrc
LIBDIR := lib
BINSRC := src
BINDIR := bin
INCDIR := include
CC := gcc
CFLAGS := -Wall -Wextra -O2
LDFLAGS :=
TARGETS := $(BINDIR)/main.out $(LIBDIR)/libmyfunc.a
LIBOBJS := $(LIBSRC)/myfunc.o
.PHONY: all clean
all: $(TARGETS)
clean:
rm -f $(TARGETS) $(BINSRC)/*.o $(LIBSRC)/*.o
$(LIBSRC)/%.o: $(LIBSRC)/%.c
$(CC) $(CFLAGS) -I$(INCDIR) $(LDFLAGS) -c $^ -o $#
$(BINSRC)/%.o: $(BINSRC)/%.c
$(CC) $(CFLAGS) -I$(INCDIR) $(LDFLAGS) -c $^ -o $#
$(LIBDIR)/libmyfunc.a: $(LIBOBJS)
$(AR) -rcv $# $^
$(BINDIR)/main.out: $(BINSRC)/main.o $(LIBDIR)/libmyfunc.a
$(CC) $(CFLAGS) -I$(INCDIR)/ $(BINSRC)/main.o $(LDFLAGS) -L$(LIBDIR) -lmyfunc -o $#
Or, if you prefer to put temporary object files into a separate directory, say build/, then
CC := gcc
CFLAGS := -Wall -Wextra -O2
LDFLAGS :=
BUILDDIR := build
INCDIR := include
SRCDIR := src
BINDIR := bin
LIBDIR := lib
MAINOBJS := $(BUILDDIR)/main.o
LIBOBJS := $(BUILDDIR)/myfunc.o
TARGETS := $(BINDIR)/main $(LIBDIR)/libmyfunc.a
.PHONY: all clean
all: $(TARGETS)
clean:
rm -f $(TARGETS) $(MAINOBJS) $(LIBOBJS) $(BUILDDIR)/*
$(LIBDIR)/libmyfunc.a: $(LIBOBJS)
$(AR) -rcv $# $(LIBOBJS)
$(BUILDDIR)/%.o: $(SRCDIR)/%.c
$(CC) $(CFLAGS) -I$(INCDIR) -c $^ -o $#
$(BINDIR)/main: $(MAINOBJS) $(LIBDIR)/libmyfunc.a
$(CC) $(CFLAGS) -I$(INCDIR) $(MAINOBJS) $(LDFLAGS) -L$(LIBDIR) -lmyfunc -o $#
This has the benefit of keeping the source directory unchanged.
This is the following Makefile at issue:
#
# Compiler flags
#
CC = gcc
CFLAGS = -Wall -Werror -Wextra
#
# Project files
# example -
# SRCS = hash_table.c linked_list.c utils.c common.c business_logic.c user_interface.c
# SRCS = test/gc_test.c src/gc.c
SRCS := $(shell find . -name "*")
OBJS = $(SRCS:.c=.o)
EXE = output.out
FILENAMES := $(shell find . -type f -name "*.c" -printf "%f\n")
FILENAMES_OUT = $(FILENAMES:.c=.o)
#
# Default build settings
#
BUILDDIR = build
BUILDCFLAGS = -g -O0
BUILDEXE = $(BUILDDIR)/$(EXE)
BUILDOBJS = $(addprefix $(BUILDDIR)/, $(FILENAMES_OUT))
# Rules for default build
all: clean build
build: $(BUILDEXE)
$(BUILDEXE): $(BUILDOBJS)
$(CC) $(CFLAGS) $(BUILDCFLAGS) -o $(BUILDEXE) $^ -lcunit
$(BUILDDIR)/%.o: %.c
$(CC) $(CFLAGS) $(BUILDCFLAGS) -c $< -o $#
memtest: $(BUILDEXE)
valgrind --leak-check=full ./$<
#
# Other rules
#
clean:
mkdir -p $(BUILDDIR)
PROBLEM -> make: *** No rule to make target `build/gc_test.o', needed by `build/output.out'. Stop.
PROJECT TREE
.
├── build
├── doc
│ └── design.md
├── Makefile
├── proj
│ ├── code_quality_report.md
│ ├── deviations.md
│ ├── individual_reflection.md
│ ├── team_reflection.md
│ └── test_report.md
├── README.md
├── src
│ ├── gc.c
│ └── headers
│ └── gc.h
└── tests
└── gc_test.c
The issue itself happens in $(BUILDEXE): $(BUILDOBJS) where the dependencies are gc_test.c gc.c. Those dependencies SHOULD get caught in the function below it, because it's input is all the .c files in the build directory. Those files SHOULD get properly matched and then compiled to .o files which then should climb up the tree and produce an executable. I'm confused because $(BUILDOBJS) should be the same as $(BUILDDIR)/%.o.
I'm new to making Makefiles, but I want to get better at it. Please point out better naming conventions or terminology that could have been used better for this post. Thanks!
The problem is here:
FILENAMES := $(shell find . -type f -name "*.c" -printf "%f\n")
This is wrong because -printf "%f\n" prints only the filenames, without any path. You're losing all information about the path where files are found, so how can make find them?
You should change this to simply -print then it will work.
I have a more or less complicated LKM. This LKM contains the directories as shown below:
├── core.c
├── headers
│ ├── core.h
│ └── server.h
├── include
│ ├── headers
│ │ └── utils.h
│ └── utils.c
├── libs
│ ├── headers
│ │ └── syscalltable.h
│ └── syscalltable.c
├── LICENSE
├── Makefile
├── README.md
├── server.c
├── src
│ ├── getdents_hook.c
│ ├── headers
│ │ ├── getdents_hook.h
│ │ ├── module_hiding.h
│ │ ├── network_keylog.h
│ │ ├── packet_hiding.h
│ │ ├── port_knocking.h
│ │ ├── privilege_escalation.h
│ │ └── socket_hiding.h
│ ├── module_hiding.c
│ ├── network_keylog.c
│ ├── packet_hiding.c
│ ├── port_knocking.c
│ ├── privilege_escalation.c
│ └── socket_hiding.c
└── TASKS.md
It seems like a overhead for this small project, but the goal was to create a LKM that could be extended easily.
The problem lies in the Makefile. As every header file is in its respective headers subdirectory, I created a Makefile that looks like this:
# Module name
ROOTKIT = rootkit
# Build
CC = gcc
PWD = $(shell pwd)
UNAME = $(shell uname -r)
MODULEDIR = /lib/modules/$(UNAME)
BUILDDIR = $(MODULEDIR)/build
KERNELDIR = $(MODULEDIR)/kernel
# Headers
CORE_H = headers
LIBS_H = libs/headers
SRCS_H = src/headers
INCL_H = include/headers
# Files
CORE = $(wildcard *.c)
CORE_OBJS = $(patsubst %.c, %.o, $(CORE))
LIBS = $(wildcard libs/*.c)
LIBS_OBJS = $(patsubst %.c, %.o, $(LIBS))
INCL = $(wildcard include/*.c)
INCL_OBJS = $(patsubst %.c, %.o, $(INCL))
# Exception for this one file
NETW = src/network_keylog.c
NETW_OBJS = src/network_keylog.o
SRC = $(wildcard src/*.c)
SRCS = $(filter-out $(NETW), $(SRC))
SRCS_OBJS = $(patsubst %.c, %.o, $(SRCS))
# Objects
# $(CORE_OBJS): $(CORE)
# $(CC) -c -o $# $< -I$(CORE_H) -I$(INCL_H)
# $(LIBS_OBJS): $(LIBS)
# $(CC) -c -o $# $< -I$(LIBS_H) -I$(INCL_H)
# $(SRCS_OBJS): $(SRCS)
# $(CC) -c -o $# $< -I$(SRCS_H) -I$(INCL_H)
# $(NETW_OBJS): $(NETW)
# $(CC) -c -o $# $< -I$(SRCS_H) -I$(CORE_H) -I$(INCL_H)
# Module
obj-m += $(ROOTKIT).o
$(ROOTKIT)-y = $(CORE_OBJS) $(LIBS_OBJS) $(SRCS_OBJS) $(NETW_OBJS)
EXTRA_CFLAGS = -I$(CORE_H) -I$(INCL_H) -I$(LIBS_H) -I$(SRCS_H)
# Recipes
all:
$(MAKE) -C $(BUILDDIR) M=$(PWD) modules
load:
insmod $(KERNELDIR)/net/ipv4/netfilter/nf_reject_ipv4.ko
insmod $(KERNELDIR)/net/ipv6/netfilter/nf_reject_ipv6.ko
insmod rootkit.ko
clean:
$(MAKE) -C $(BUILDDIR) M=$(PWD) clean
However I only get this error:
make -C /lib/modules/4.9.0-3-amd64/build M=/home/croemheld/Repositories/lkm-rootkit modules
make[1]: Verzeichnis „/usr/src/linux-headers-4.9.0-3-amd64“ wird betreten
/bin/sh: 1: Syntax error: "(" unexpected
[...]
I know that the Makefile executes its procedure in a shell, but I can't understand what command the shell can't execute or why this is failing in general. Or is this approach completely wrong?
EDIT: Seems like I missed a missing $ in a -I flag...
However, it still does not compile. The problem is that every file includes the utils.h in include/headers/, and I don't know how to specify the compile procedure so that it works.
Currently:
all source files include my own header files (meaning in the *.c files are only includes like "xyz.h" and in the headers only <....h >)
the core.c and server.c include all other header files.
every source file includes the utils.h header and its "own" header file, except for network_keylog.c: this one also includes server.h.
Current output:
make -C /lib/modules/4.9.0-3-amd64/build M=/home/croemheld/Repositories/lkm-rootkit modules
make[1]: Verzeichnis „/usr/src/linux-headers-4.9.0-3-amd64“ wird betreten
CC [M] /home/croemheld/Repositories/lkm-rootkit/src/network_keylog.o
/home/croemheld/Repositories/lkm-rootkit/src/network_keylog.c:1:19: fatal error: utils.h: Datei oder Verzeichnis nicht gefunden
#include "utils.h"
^
compilation terminated.
/usr/src/linux-headers-4.9.0-3-common/scripts/Makefile.build:298: die Regel für Ziel „/home/croemheld/Repositories/lkm-rootkit/src/network_keylog.o“ scheiterte
make[4]: *** [/home/croemheld/Repositories/lkm-rootkit/src/network_keylog.o] Fehler 1
I'm working on a C project, and I decided to put the source code and its objects in different directories. The root directory has something like that:
SmartC ▶ tree -L 1
.
├── built
├── doc
├── Makefile
├── README.md
├── src
├── tests
└── trash
So, inside both src and built directories, I put two others Makefiles to do the compile and link jobs.
The src directory (where I put the source code) has the following structure:
src
├── graph.c
├── graph.h
├── list.c
├── list.h
├── main.c
├── Makefile
├── node.c
├── node.h
├── tree.c
├── tree.h
└── types
├── complex.c
├── complex.h
├── matrix.c
└── matrix.h
and the built has the same structure, but it is intended to store all objects made by compilation.
My question is about my src/Makefile:
BINDIR = ../built/src
CC = gcc
CFLAGS = -g -Wall -O3
OBJECTS = \
$(BINDIR)/main.o \
$(BINDIR)/node.o \
$(BINDIR)/list.o \
$(BINDIR)/graph.o \
$(BINDIR)/tree.o \
$(BINDIR)/types/complex.o \
$(BINDIR)/types/matrix.o \
compile: $(OBJECTS)
$(BINDIR)/%.o: %.c
$(CC) -c $< -o $# $(CFLAGS)
This Makefile creates all the objects of the source code, inside src directory, and move them to built/src. But, every time I create a new source code file (*.c), I have to put the name of its object in this makefile, so it can be compiled. I'd like to do an automatic search, inside the src directory, and fill the "OBJECTS" variable with this search.
Is anyone has some idea of how to accomplish this? I mean, automatic search for source code inside an specific directory?
I even accept any other strategy rather than what I'm making.
=========== Answer ===============
I got the tip (in comments) about wildcards. So I did. Here is the solution I found.
src/Makefile
BINDIR = ../built/src
CC = gcc
CFLAGS = -g -Wall -O3
OBJECTS := $(patsubst %.c,$(BINDIR)/%.o,$(wildcard *.c */*.c))
compile: $(OBJECTS)
$(BINDIR)/%.o: %.c
$(CC) -c $< -o $# $(CFLAGS)
EDIT [Solved]
I like to do the following.
Create Variables to Each Directory of the Project
SRCDIR = src
OBJDIR = obj
LIBDIR = lib
DOCDIR = doc
HDRDIR = include
CFLAGS = -g -Wall -O3
Get Only the Internal Structure of SRCDIR Recursively
STRUCTURE := $(shell find $(SRCDIR) -type d)
Get All Files inside the STRUCTURE Variable
CODEFILES := $(addsuffix /*,$(STRUCTURE))
CODEFILES := $(wildcard $(CODEFILES))
Filter Out Only Specific Files
# Filter Only Specific Files
SRCFILES := $(filter %.c,$(CODEFILES))
HDRFILES := $(filter %.h,$(CODEFILES))
OBJFILES := $(subst $(SRCDIR),$(OBJDIR),$(SRCFILES:%.c=%.o))
# Filter Out Function main for Libraries
LIBDEPS := $(filter-out $(OBJDIR)/main.o,$(OBJFILES))
Now it is Time to create the Rules
compile: $(OBJFILES)
$(OBJDIR)/%.o: $(addprefix $(SRCDIR)/,%.c %.h)
$(CC) -c $< -o $# $(CFLAGS)
With this approach, you can see that I'm using the STRUCTURE variable only to get the files inside the SRCDIR directory, but it can be used for others purposes as well, like mirror the SRCDIR inside OBJDIR once STRUCTURE stores only the internal sub-directories. It is quite useful after clean operations like:
clean:
-rm -r $(OBJDIR)/*
NOTE: The compile rule only works well if for each *.c there is the corresponding *.h file (with the same base name, I mean).