Most Linux apps are compiled with:
make
make install clean
As I understand it, the make command takes names of build targets as arguments. So for example install is usually a target that copies some files to standard locations, and clean is a target that removes temporary files.
But what target will make build if no arguments are specified (e.g. the first command in my example)?
By default, it begins by processing the first target that does not begin with a . aka the default goal; to do that, it may have to process other targets - specifically, ones the first target depends on.
The GNU Make Manual covers all this stuff, and is a surprisingly easy and informative read.
To save others a few seconds, and to save them from having to read the manual, here's the short answer. Add this to the top of your make file:
.DEFAULT_GOAL := mytarget
mytarget will now be the target that is run if "make" is executed and no target is specified.
If you have an older version of make (<= 3.80), this won't work. If this is the case, then you can do what anon mentions, simply add this to the top of your make file:
.PHONY: default
default: mytarget ;
References:
https://www.gnu.org/software/make/manual/html_node/How-Make-Works.html
GNU Make also allows you to specify the default make target using a special variable called .DEFAULT_GOAL. You can even unset this variable in the middle of the Makefile, causing the next target in the file to become the default target.
Ref: The Gnu Make manual - Special Variables
bmake's equivalent of GNU Make's .DEFAULT_GOAL is .MAIN:
$ cat Makefile
.MAIN: foo
all:
#echo all
foo:
#echo foo
$ bmake
foo
See the bmake(1) manual page.
Related
I have an AVR8 GCC application that can be built with a standard makefile. Because some folks who want to build the application don't want to set up make and such (or have trouble doing so), I also have figured out how to set the project up so it can be compiled from the Arduino IDE as well.
All is working.
But, I normally set some items in the makefile, like the version number and such, but creating the VERSION string in the makefile and passing it as a define into each source file compilation. But, when run from the Arduino IDE, that step is obviously not occurring. So, I have to create a second #define in the Arduino sketch stub to recreate the define.
This means when I update the version, I need to do so in 2 places, in the makefile and in the source file.
The easy option is to simply move the VERSION creation to the source file, where both can use it. And, I'm OK doing that, but
The makefile actually needs the version information, both to create the right filename (think app_v1.2.3.4.bin) and embed the version number into the bin file since it is used by the boot-loader (if requested) to ensure the version the boot-loader flashes is newer than the one already in FLASH. So, if I move the VERSION, RELEASE, MODIFICATION, etc. defines into the C code, I need to find a way to pull them back into the makefile.
I tried using the file read operations in the makefile, but they seem to ignore:
#define VERSION 0
with the prefaced '#' char.
I see there's some options to run sed/awk/etc, in bash, but I don't want to make too many assumptions on the environment, and the makefile currently runs on Windows as well as Unix/Linux without any differences.
I tried a few stack overflow examples, but nothing seems to yield those 4 numbers from any file, .h or otherwise.
I'm OK with creating version.h with just:
#define VERSION 0
#define RELEASE 1
#define MODIFICATION 2
#define FIX 4
If I can read it into the makefile and create the variables I need.
Jim
You may take a look at gmtt which was designed exactly with you use case in mind. In gmtt the following should read and analyze your header file:
include gmtt.mk
# create a 3-column table from the header file. The first column is just the "#define"
VNR_TABLE := 3 $(file < version.h)
# Extract the values from the table: select column 3 from VNR_TABLE where column 2 equals a string constant.
# Be careful not to introduce spaces in the compare!
VER := $(call select,3,$(VNR_TABLE),$$(call str-eq,$$2,VERSION))
REL := $(call select,3,$(VNR_TABLE),$$(call str-eq,$$2,RELEASE))
MODF := $(call select,3,$(VNR_TABLE),$$(call str-eq,$$2,MODIFICATION))
FIX := $(call select,3,$(VNR_TABLE),$$(call str-eq,$$2,FIX))
I couldn't test it but I think you get the idea.
PS: using a GNUmake library just means placing the included file alongside the makefile.
I think in this case you can use the ‘file’ function of makefiles.
It allows you to write (with > specifier) or read (with < specifier) to/from files. Then you can trim (with filter-out) your variables inside your makefile.
Source: https://www.gnu.org/software/make/manual/html_node/File-Function.html#File-Function
You can use GNU make's $(shell ...) function to extract the macro expansions. Assuming VERSION is defined in src.c and tokens are delimited by spaces (not tabs):
VERSION := $(shell sed -n -e "s/^\#define VERSION *\(.*\)/\1/p" src.c)
.PHONY: all
all:
#echo VERSION=$(VERSION)
Having built my application, initially using debug, I now move to make it production ready. I have changed my compile options from
-c -W"c,debug,LP64,sscomm,dll"
to
-c -s -W"c,LP64,sscomm,dll"
which reduces the size of the resultant executable to 60% of the debug version.
I changed my link options from
-W"l,LP64,DYNAM=DLL"
to
-s -W"l,LP64,DYNAM=DLL"
which further reduces the size of the resultant executable to 20% of the original debug version.
So it certainly seems to be doing something. But when I view the executable, I can still see all the function name eye-catchers in the executable, and when I force an abend, the CEEDUMP generated still shows all the function names in that file. I expected -s to remove all symbolic information.
So my question is "how do I remove all symbolic information?"
In addition, once linked with -s I can no longer copy the module to an MVS dataset, from the USS file where it is generated. I use the following command:-
cp -X prog "//'ME.USER.LOAD(PROG)'"
which fails with:-
IEW2523E 3702 MEMBER *NULL* IDENTIFIED BY DDNAME /0000002 IS NOT AN EDITABLE
MODULE AND CANNOT BE INCLUDED.
IEW2510W 3704 ENTRY OFFSET 0 IN MODULE *NULL* IDENTIFIED BY DDNAME /0000002
DOES NOT EXIST IN A VALID SECTION.
cp: FSUMF140 IEWBIND function "INCLUDE" failed with return code 8 and reason code 83000505
This error message seems to say that I need the EDIT linkage option, but if I add that in, it appears to negate the step of using -s on the link, as the size goes back up to 60% of the debug version size.
So my second question is, "how do I copy the file to an MVS dataset and also remove symbolic information?"
Maybe there is a subsequent step that I can take to drive the binder again to remove symbolic information from the USS file and from the MVS dataset after the copy?
You can use COMPRESS compiler option and to some extent COMPACT. The COMPRESS option will suppress emitting function names in control blocks, while the COMPACT option will influence the compiler optimization choices to favor smaller object size.
Even though you are compiling and linking your executable in USS, you do not need to produce the executable in USS and then copy it to a data set. You can put your executable straight into the data set by using -o "//'ME.USER.LOAD(PROG)'" syntax. Just make sure your output data set is a PDSE.
Since you are compiling and linking in USS, you should use the xlc utility with -q syntax for compiler options as this syntax avoids the use of parenthesis which have special meaning in shell.
I have written a c program. I want to pipe the program and I want to make it look meaningful. So instead of writing ./a.out each time, I want to name it changetext. To achieve that, I compiled my program following way: gcc -o changetext myprog.c. To the best of my knowledge, this should replace the use of ./a.out and changetext should do that instead. But I'm getting command not found. I am new to c and unix environment. Any suggestion appreciated.
As I said in a comment, you can either put a dot slash (./) in front of the executable to run it
./changetext
Or you put in in a directory that is referenced in the PATH environment variable. A nice explanation of this safety feature can be found here (thanks to rubenvb):
http://www.linfo.org/dot_slash.html
It says that this is more or less to distinguish built-in commands from user-written commands with the same name. I am not convinced though. The shell could simply prefer built-in names to user-supplied ones, and look in the current directory as well as in the PATH.
But this is the *nix way.
In order to compile and run a program such as your changetext with just the command chanhetext, you must put the binary in a directory listed in your PATH environment variable. It is recommended that you put programs that you made for your own use in the ~/bin/ directory. The command you would use to accomplish this would be the following, assuming ~/bin/ already exists:
gcc -o ~/bin/changetext myprog.c
If it does not exist, you can simply create it, then log out and back in.
If you are tired of doing the ./ before the program name you can always make an alias such as
alias a='./a.out' or alias changetext='./changetext'
this just basically look for everytime you type changetext or a and then replaces it to have the ./ infront of it
I am new in Makefile. I have wrote hello.c and when I do "make hello" then it gives executable named as "hello". Internally it showing "cc hello.c -o hello". But without Makefile how make works? How make is gives executable as same name as source?
make has a database of built in rules. These rules include recipes for a number of common operations.
The GNU Make Manual covers (some at least) of these recipes in the Catalogue of Built-Inf Rules section.
Additionally, the output from the -p/--print-data-base option will show you all of the rules/recipes and variables that make has built-in.
the make command of your compiler will, if no further arguments are given and no makefile is present, use default parameters. Default parameters are, in the case of your hello.c (a normal c file) and your compiler settings (presumably fresh from install) to make an executable with the same name as the input file.
Thats just how the compiler is made.
I tried to use a make file in code::blocks but I am doing it wrong. I have the version installed with the compilers included. http://sourceforge.net/projects/codeblocks/files/Binaries/10.05/Windows/codeblocks-10.05mingw-setup.exe/download. What do I do with the make file? It starts with:
CC=gcc
best, US
You don't tend to execute the make file itself, rather you execute make, giving it the make file as an argument:
make -f pax.mk
If your make file is actually one of the standard names (like makefile or Makefile), you don't even need to specify it. It'll be picked up by default (if you have more than one of these standard names in your build directory, you better look up the make man page to see which takes precedence).
As paxdiablo said make -f pax.mk would execute the pax.mk makefile, if you directly execute it by typing ./pax.mk, then you would get syntax error.
Also you can just type make if your file name is makefile/Makefile.
Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
Check out more about makefile at this Tutorial : Basic understanding of Makefile