This question already has answers here:
makefile:4: *** missing separator. Stop
(17 answers)
Closed 3 years ago.
I keep getting this error while I try to run the code on my raspberry pi, I dont know what has caused this:
CC = gcc
CFLAGS = -Wall -O0 -std=gnu99 -I/usr/local/include -g
LDFLAGS = -L/usr/local/lib -pthread -lm -lwiringPi
FUSEFLAGS = `pkg-config fuse --cflags --libs`
SOURCES = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SOURCES))
BINS = $(SOURCES:.c=)
all: $(PROGS)
%: %.c
$(CC) $< $(CFLAGS) $(LDFLAGS) -o $# $(FUSEFLAGS)
clean:
$(RM) *.o *.a $(BINS)
this gives the following error:
Makefile:14: *** missing separator. Stop.
when I use make to run my code. my make was working before I am not sure what has caused this happend all the sudden!
CC = gcc
CFLAGS = -Wall -O0 -std=gnu99 -I/usr/local/include -g
LDFLAGS = -L/usr/local/lib -pthread -lm -lwiringPi
FUSEFLAGS = `pkg-config fuse --cflags --libs`
SOURCES = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SOURCES))
BINS = $(SOURCES:.c=)
all: $(PROGS)
%: %.c
<___T___A___B___>$(CC) $< $(CFLAGS) $(LDFLAGS) -o $# $(FUSEFLAGS)
clean:
<___T___A___B___>$(RM) *.o *.a $(BINS)
Where I have written <___T___A___B___>, there should be 1 tab and not spaces !
Related
I want to compile a C program from GitHub on Windows 7 and get an error that a file is not found. I have installed MinGW Make and its dependancies. I think maybe this program is only intended to run on Linux.
The Console output:
E:\work-c\iso2opl-clone\iso2opl>make
gcc -std=gnu99 -pedantic -usr\include -usr\local\inc
lude -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE -c isofs.c -o isofs.o
process_begin: CreateProcess(NULL, gcc -std=gnu99 -pedantic -F:\programs\mingw\i
nclude -F:\programs\mingw\local\include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SO
URCE -c isofs.c -o isofs.o, ...) failed.
make (e=2): Le fichier spécifié est introuvable.
make: *** [isofs.o] Erreur 2
the makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -I/usr/include -I/usr/local/include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE
#CFLAGS += -DDEBUG
ifeq ($(_WIN32),1)
CFLAGS += -D_WIN32
endif
OBJS = isofs.o \
iso2opl.o
all: $(TARGET)
rm-elf:
-rm -f $(TARGET) $(OBJS)
$(TARGET): $(OBJS)
$(CC) $(OBJS) -o $(TARGET) $(LIBS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%.o: %.cpp
$(CC) $(CFLAGS) -c $< -o $#
clean:
rm -r $(OBJS) $(TARGET)
I don't know maybe the paths are wrongs.
Best Regards
Try to run the make in the MSYS2 shell (https://www.msys2.org/). I was able to build the sources from https://github.com/arcadenea/iso2opl without issue.
hi im trying to create a shared object for my native library to be accessed by my java project but when i run the makefile i get the error unable to link
here's my makefile
LIB_FILE = ../lib/libpktartintf.so
SRCS := $(wildcard *.c)
OBJS := $(SRCS:.c=.o)
DEPS := $(OBJS:.o=.d)
CC = gcc
INCFLAGS = -I../include
CFLAGS += $(INCFLAGS) -Wall -MMD -MP
LDFLAGS = -shared
$(LIB_FILE): $(OBJS)
$(CC) -c $(LDFLAGS) $(CFLAGS) -o $# $<
.PHONY: clean
clean:
rm -f *.o *.d $(LIB_FILE)
-include $(DEPS)
when I "make" it im getting the following error
gcc -c -shared -I../include -Wall -MMD -MP -o ../lib/libpktartintf.so pktartintf.o
gcc: warning: pktartintf.o: linker input file unused because linking not done
any idea why
I'm not an expert of Makefile.
In my program I'm using hashtables of glib.h so in my Makefile I wrote this:
exec: bin/test
bin/test
clean:
rm -f build/* bin/*
CFLAGS = -g -Wall -Wpedantic -Wno-padded -O $(shell pkg-config --cflags --libs glib-2.0)
INCLUDES = include/*.h
COMMON_DEPS = $(INCLUDES) Makefile
build/%.o: src/%.c $(COMMON_DEPS)
$(CC) $(CFLAGS) -c $< -o $#
bin/test: /* functions.o*/ $(COMMON_DEPS)
$(CC) -o bin/test /* functions.o*/
But when I execute the Makefile I receive a list of these error messages:
...
functions.c: undefined reference to "g_str_hash"
functions.c: undefined reference to "g_str_equal"
...
I don't understand why
At the end I solved it in this way:
exec: bin/test
bin/test
clean:
rm -f build/* bin/*
CFLAGS = -g -Wall -Wpedantic -Wno-padded -O $(shell pkg-config --cflags glib-2.0)
LFLAGS = $(shell pkg-config --libs glib-2.0)
INCLUDES = include/*.h
COMMON_DEPS = $(INCLUDES) Makefile
build/%.o: src/%.c $(COMMON_DEPS)
$(CC) $(CFLAGS) -c $< -o $#
bin/test: /*functions.o */ $(COMMON_DEPS)
$(CC) -o bin/test /*functions.o */ $(LFLAGS)
The crux of the problem is that you're including the link flags in the compile command rather than the link command itself.
Remove --libs glib-2.0 from CFLAGS and add it to a new variable LFLAGS that can be used on the link line...
exec: bin/test
bin/test
clean:
rm -f build/* bin/*
CFLAGS = -g -Wall -Wpedantic -Wno-padded -O $(shell pkg-config --cflags glib-2.0)
LFLAGS = $(shell pkg-config --libs glib-2.0)
INCLUDES = include/*.h
COMMON_DEPS = $(INCLUDES) Makefile
build/%.o: src/%.c $(COMMON_DEPS)
$(CC) $(CFLAGS) -c $< -o $#
bin/test: /* functions.o*/ $(COMMON_DEPS)
$(CC) $(LFLAGS) -o bin/test /* functions.o*/
[Note: I've left the rest of the makefile untouched but the dependency specification for bin/test does look very odd.]
I am trying to compile a GTK+ example using make, but when I run it, the terminal says "make: *** No rule to make target 'all'. Stop."
However, when I compile by typing the following, it compiles successfully.
gcc -g -Wall -o exampleapp main.c exampleapp.c exampleapp.h exampleappwin.c exampleappwin.h -export-dynamic `pkg-config --cflags --libs gtk+-3.0`
Here's what I put in my make file:
NAME=exampleapp
CFLAGS=-g -Wall -o $(NAME)
GTKFLAGS=-export-dynamic `pkg-config --cflags --libs gtk+-3.0`
SRCS= \
main.c \
exampleapp.c exampleapp.h \
exampleappwin.c exampleappwin.h
CC=gcc
all: main
main: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(GTKFLAGS)
clean:
/bin/rm -f $(NAME)
Is something wrong with my make file? If so, how can I correct it?
You are missing some tabs in the rule section of your Makefile.
It should look like:
all: main
main: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(GTKFLAGS)
clean:
/bin/rm -f $(NAME)
Note that the action lines must be indented with a literal tab character, not with spaces. (Stack Overflow converts the tab to four spaces -- don't just copy and paste!)
there are a few problems with the posted makefile.
Suggest using the following, which has recipe lines properly indented with a <tab> and generates macros using := so they are not re-evaluated every time they are referenced in the makefile.
This sample makefile also corrects the recipes for compiling and linking
NAME=exampleapp
CFLAGS := -g -Wall -Wextra -pedantic -std=gnu11 -c
GTKFLAGS := -export-dynamic `pkg-config --cflags --libs gtk+-3.0`
SRCS := \
main.c \
exampleapp.c \
exampleappwin.c
OBJS := $(SRCS:.c=.o)
HDRS := exampleapp.h examplappwin.h
CC := /usr/bin/gcc
RM := /bin/rm
.PSEUDO: all clean
all: $(NAME)
%.o:%.c $(HDRS)
<tab>$(CC) $(CFLAGS) -o $# $< -I.
$(NAME): $(OBS)
<tab>$(CC) $> $(GTKFLAGS) -o $#
clean:
<tab>$(RM) -f $(NAME) $(OBJS)
Note: the <tab> must be replaced in the actual file with a tab character
I got a question, at school we compile C with this command :
clang -o filename -O0 -g -std=c99 -Wall -Wextra filename.c
and I'd like to make an alias such as clang-c which contains all these options
I tried also clang-c='clang -O0 -g -std=c99 -Wall -Wextra' but impossible like this to set the name of the output file..
Do you have any idea ?
I give you a Makefile example:
INCPATH = includes/
CC = gcc
CFLAGS = -I $(INCPATH) -Wall -Wextra -pedantic -fPIC -O2
LDFLAGS = -shared
TARGET = libmy_malloc_$(HOSTTYPE).so
LINK_NAME = libmy_malloc.so
SRC = malloc.c internal.c
OBJ = $(SRC:.c=.o)
RM = rm -vf
LN = ln
all: $(TARGET)
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
$(LN) -s $(TARGET) $(LINK_NAME)
clean:
$(RM) $(OBJ)
fclean: clean
$(RM) $(TARGET) $(LINK_NAME)
re: fclean all
You can set all of your flag on the CFLAGS line!