I got a question, at school we compile C with this command :
clang -o filename -O0 -g -std=c99 -Wall -Wextra filename.c
and I'd like to make an alias such as clang-c which contains all these options
I tried also clang-c='clang -O0 -g -std=c99 -Wall -Wextra' but impossible like this to set the name of the output file..
Do you have any idea ?
I give you a Makefile example:
INCPATH = includes/
CC = gcc
CFLAGS = -I $(INCPATH) -Wall -Wextra -pedantic -fPIC -O2
LDFLAGS = -shared
TARGET = libmy_malloc_$(HOSTTYPE).so
LINK_NAME = libmy_malloc.so
SRC = malloc.c internal.c
OBJ = $(SRC:.c=.o)
RM = rm -vf
LN = ln
all: $(TARGET)
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
$(LN) -s $(TARGET) $(LINK_NAME)
clean:
$(RM) $(OBJ)
fclean: clean
$(RM) $(TARGET) $(LINK_NAME)
re: fclean all
You can set all of your flag on the CFLAGS line!
Related
I accidentally deleted the %.o: %.c section in my Makefile, but it still works fine; could somebody let me know WHY?
Here's my Makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -Wall -O3
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c,%.o,$(SRCS))
myProgram: $(OBJS)
$(CC) -o $# -O3 $^
.PHONY: clean
clean:
rm -f myProgram *.o *.c~ *.h~ *.swp
and here's the output of clean make:
$ make clean; make
rm -f myProgram *.o *.c~ *.h~ *.swp
gcc -std=gnu99 -pedantic -Wall -O3 -c -o anotherFile.o anotherFile.c
gcc -std=gnu99 -pedantic -Wall -O3 -c -o oneFile.o oneFile.c
gcc -o myProgram -O3 anotherFile.o oneFile.o
I want to compile a C program from GitHub on Windows 7 and get an error that a file is not found. I have installed MinGW Make and its dependancies. I think maybe this program is only intended to run on Linux.
The Console output:
E:\work-c\iso2opl-clone\iso2opl>make
gcc -std=gnu99 -pedantic -usr\include -usr\local\inc
lude -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE -c isofs.c -o isofs.o
process_begin: CreateProcess(NULL, gcc -std=gnu99 -pedantic -F:\programs\mingw\i
nclude -F:\programs\mingw\local\include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SO
URCE -c isofs.c -o isofs.o, ...) failed.
make (e=2): Le fichier spécifié est introuvable.
make: *** [isofs.o] Erreur 2
the makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -I/usr/include -I/usr/local/include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE
#CFLAGS += -DDEBUG
ifeq ($(_WIN32),1)
CFLAGS += -D_WIN32
endif
OBJS = isofs.o \
iso2opl.o
all: $(TARGET)
rm-elf:
-rm -f $(TARGET) $(OBJS)
$(TARGET): $(OBJS)
$(CC) $(OBJS) -o $(TARGET) $(LIBS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%.o: %.cpp
$(CC) $(CFLAGS) -c $< -o $#
clean:
rm -r $(OBJS) $(TARGET)
I don't know maybe the paths are wrongs.
Best Regards
Try to run the make in the MSYS2 shell (https://www.msys2.org/). I was able to build the sources from https://github.com/arcadenea/iso2opl without issue.
I have the following make file. The problem is that even if there are no changes in the two .cpp files, it still run all the commands on prompt. Everything else is working fine.
all: hello1
hello1: make func
gcc hellomake.o hellofunc.o -o hello -I.
make: hellomake.c
gcc -c hellomake.c
func: hellofunc.c
gcc -c hellofunc.c
clean:
rm -rf *o hello
run:
./hello
Here is a sample Makefile that you can modifiy (especially CFLAGS section), and in won't relink
NAME = xxx
SRCS = xxx.c
OBJS = $(SRCS:.c=.o)
CC = gcc
RM = rm -rf
CFLAGS += -W -Wall -Wextra
CFLAGS += -O2
CFLAGS += -ansi -pedantic
CFLAGS += -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE
all: $(NAME)
$(NAME): $(OBJS)
$(CC) $(OBJS) -o $(NAME)
clean:
$(RM) $(OBJS)
fclean: clean
$(RM) $(NAME)
re: fclean all
.PHONY: all clean fclean re
.PHONY allow to differentiate eventual file names and rule names
You need to replace the .c to .o in the targets as described below
make: hellomake.o
gcc -c hellomake.c
func: hellofunc.o
gcc -c hellofunc.c
This is my first post in this forum. Sorry for bothering but I've been looking for something similar and strangely I couldn't find it. Here's the issue.
I have three (main) files with no headers and I want to compile them either at once (if I simply type "make") or one by one (if I specify the name of the file with no extension). So I built my makefile but something is wrong in the command
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
where I got this error
make: *** No rule to make target....
here's the complete file
.SUFFIXES: .c
ROOT = $(addprefix $(PWD), /)
BUILDS_DIR = $(addprefix $(ROOT), builds/)
SRCS_DIR = $(addprefix $(ROOT), src/)
SRCS = $(wildcard $(SRCS_DIR)*.c)
TARGETS = ${SRCS:$(SRCS_DIR)%.c=%}
EXES = ${addprefix $(BUILDS_DIR), $(TARGETS)}
CC = gcc
CFLAGS = -Wall -O3
RM = rm -f
.PHONY: all $(TARGETS) clean
all: $(TARGETS)
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) \
$< \
-o $#
#echo -e "\n\n\t\t*** Compile successfully! ***\n" ;
clean:
$(RM) $(EXES) \
$(SRCS_DIR)*~
#echo -e "\n\n\t\t*** Cleanup complete! ***\n"
Where am I wrong? I guess the answer is very silly and probably based on a basic error.
thanks in advance
Assuming GNU Make (since you use its syntax).
The, or the first, problem is that you are trying to rewrite the target static pattern incorrectly, by trying to concatenate the target directory to the pattern, rather than simply using the target's filename.
You had:
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $#
The solution is to use add the directory path on the command line
$(TARGETS): % : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $(BUILDS_DIR)$#
Lets assume that your three source files are file1.c, file2.c and file3.c. I would created the makefile to look like this (assuming GNU make)
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
file1 : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
file2 : file2.c
$(CC) $(CFLAGS) -c file2.c -o file2.o
file3 : file3.c
$(CC) $(CFLAGS) -c file3.c -o file3.o
clean :
$(RM) *.o $(PROG) *.*~
A sample using this make file is (I use the -n to show what rules would be run, but not actually run them because my source files are empty files for testing.)
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file1
gcc -ansi -Wall -pedantic -c file1.c -o file1.o
We can shorten the above make file my making use of wild-cards;
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
% : %.c
$(CC) $(CFLAGS) -c $< -o $#.o
clean :
$(RM) *.o $(PROG) .~
We need to append a '.o' to the output file name so that we are creating files in the format defined by the $(OBJ) variable of the first build rule works correctly. Doing this gives the following example runs:
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file2
gcc -ansi -Wall -pedantic -c file2.c -o file2.o
BTW, I personally don't mind typing an extra two characters and I like having my target match the output of the set of rules that get run, so I would write the rules as either
file1.o : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
or
%.o :%.c
$(CC) $(CFLAGS) -c $< -o $#
Finally I strongly suspect that when we execute make or make all, we are not running the file-specific rules in the lower part of the makefile, rather we are running the the built in rule described in the GNU manual as: "n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c".
currently I'm using this command to compile my .c files in Mint
gcc -std=gnu99 -Wall -Werror filename.c -o filename [-lm]
How do I make these parameters default, perhaps include them in the make filename.c command? Thanks :)
You need to write makefile like
CC = gcc
EXEC = filename
OBJS = filename.o \
FLAGS = -std=gnu99 -Wall -Werror
LDLIBS = -lm
all: $(EXEC)
$(EXEC): $(OBJS)
$(CC) $(FLAGS) -o $# $(OBJS) $(LDLIBS)
clean:
-rm -f $(EXEC) *.o
Then run make to compile your file