I have the following make file. The problem is that even if there are no changes in the two .cpp files, it still run all the commands on prompt. Everything else is working fine.
all: hello1
hello1: make func
gcc hellomake.o hellofunc.o -o hello -I.
make: hellomake.c
gcc -c hellomake.c
func: hellofunc.c
gcc -c hellofunc.c
clean:
rm -rf *o hello
run:
./hello
Here is a sample Makefile that you can modifiy (especially CFLAGS section), and in won't relink
NAME = xxx
SRCS = xxx.c
OBJS = $(SRCS:.c=.o)
CC = gcc
RM = rm -rf
CFLAGS += -W -Wall -Wextra
CFLAGS += -O2
CFLAGS += -ansi -pedantic
CFLAGS += -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE
all: $(NAME)
$(NAME): $(OBJS)
$(CC) $(OBJS) -o $(NAME)
clean:
$(RM) $(OBJS)
fclean: clean
$(RM) $(NAME)
re: fclean all
.PHONY: all clean fclean re
.PHONY allow to differentiate eventual file names and rule names
You need to replace the .c to .o in the targets as described below
make: hellomake.o
gcc -c hellomake.c
func: hellofunc.o
gcc -c hellofunc.c
Related
I'd like that my makefile stopped linking every time I call it if the .o file is already up-to-date.
Do you have any ideas about it?
Here is my makefile:
CC = gcc
CFLAGS = -Wall -Werror -Wextra
RM = rm -f
NAME = ft_display_file
SRCS = ft_display_file.c
OBJS = ${SRCS:.c=.o}
all: $(NAME)
${NAME}: ${OBJS}
clean:
${RM} ${OBJS}
fclean: clean
${RM} $(NAME)
re: fclean all
Thanx,
Fab
I'm trying to compile my C project using clang (I'm on MacOS Monterry) and a Makefile, but I keep getting the same error from clang in the command line:
> make
gcc -c src/ji.c src/main.c -o src/ji.o
clang: error: cannot specify -o when generating multiple output files
make: *** [src/ji.o] Error 1
These are the only files I have in the project so far:
src/main.c
src/ji.c
include/ji.h
The Makefile looks like this:
cc = gcc
src = $(wildcard src/*.c)
obj = $(src:.c=.o)
exec = ji
$(exec): $(obj)
$(cc) -Iinclude $< -o build/$#
%.o: %.c
$(cc) -c $(src) -o $#
clean:
-rm src/*.o
-rm ji
From YouTube videos I've seen, this should be the ideal Makefile for the project but no matter what I change I get the error.
There are a few issues:
-Iinclude needs to be on the %.o: %.c rule command
In %.o: %.c, we don't want $(src) but rather $<
We want patsubst to get the .o list obj
The $(exec) target doesn't match the -o option
The clean doesn't match the placement of the executable
Here's a refactored version (e.g. one way to do this--there are others):
cc = gcc
src = $(wildcard src/*.c)
obj = $(patsubst %.c,%.o,$(src))
exec = build/ji
$(exec): $(obj)
mkdir -p build
$(cc) $^ -o $#
%.o: %.c
$(cc) -c $< -o $# -Iinclude
clean:
rm -f src/*.o
rm -fr build
Here's the output of make:
gcc -c src/ji.c -o src/ji.o -Iinclude
gcc -c src/main.c -o src/main.o -Iinclude
mkdir -p build
gcc src/ji.o src/main.o -o build/ji
Here's the output of make clean:
rm -f src/*.o
rm -fr build
I am trying to compile my Makefile to make library from different directories. The library is successfully compiled but I am facing the following warning
/Applications/Xcode.app/Contents/Developer/usr/bin/make -C ./libft
make[1]: Nothing to be done for `all'.
gcc -Wall -Werror -Wextra -c srcs/ft*.c libft/ft*.c -I ./includes
ar rcs libftprintf.a srcs/ft*.c libft/ft*.c*****
warning: /Applications/Xcode.app/Contents/Developer/Toolchains/Xcod
eDefault.xctoolchain/usr/bin/ranlib: archive library: libftprintf.a
the table of contents is empty (no object file members in the libr
ary define global symbols)
Please kindly advise on how to solve this warning. The structure of my directory is as follow:
steh#u90z01s01 printf % ls
Makefile includes main.c libft srcs
My Makefile is as following
NAME := libftprintf.a
CC := gcc
AR := ar rcc
CFLAGS:= -Wall -Werror -Wextra -c
SRCS = srcs/ft*.c libft/ft*.c
INCLUDES = ./includes
OBJ_FILES = $(SRCS:%.c = %.o)
$(NAME): $(OBJ_FILES)#.fr
$(MAKE) -C ./libft
$(CC) $(CFLAGS) $(SRCS) -I $(INCLUDES)
$(AR) $(NAME) $(OBJ_FILES)
all: $(NAME)
clean:
#echo "Cleaning..."
rm -rf $(NAME) ft*.o
fclean:
rm -rf $(NAME)
re: fclean all
norm:
#norminette $(LIB_FILES)
.PHONY: clean fclean all re norm
This is my latest code
NAME := libftprintf.a
CC := gcc
AR := ar rcs
CFLAGS := -Wall -Werror -Wextra -c
SRCS = ./libft/ft*.c ./srcs/ft*.c
OBJS = ft*.o
LIBFT = ./libft
INC = ./includes
# Colors
GREEN= \033[1;32m
RED= \033[1;31m
all: $(NAME)
$(NAME):
#make re -C $(LIBFT)
#$(CC) $(CFLAGS) $(SRCS) -I $(INC)
#$(AR) $(NAME) $(OBJS)
#ranlib $(NAME)
#echo "$(GREEN)ft_printf compiled!"
I accidentally deleted the %.o: %.c section in my Makefile, but it still works fine; could somebody let me know WHY?
Here's my Makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -Wall -O3
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c,%.o,$(SRCS))
myProgram: $(OBJS)
$(CC) -o $# -O3 $^
.PHONY: clean
clean:
rm -f myProgram *.o *.c~ *.h~ *.swp
and here's the output of clean make:
$ make clean; make
rm -f myProgram *.o *.c~ *.h~ *.swp
gcc -std=gnu99 -pedantic -Wall -O3 -c -o anotherFile.o anotherFile.c
gcc -std=gnu99 -pedantic -Wall -O3 -c -o oneFile.o oneFile.c
gcc -o myProgram -O3 anotherFile.o oneFile.o
I got a question, at school we compile C with this command :
clang -o filename -O0 -g -std=c99 -Wall -Wextra filename.c
and I'd like to make an alias such as clang-c which contains all these options
I tried also clang-c='clang -O0 -g -std=c99 -Wall -Wextra' but impossible like this to set the name of the output file..
Do you have any idea ?
I give you a Makefile example:
INCPATH = includes/
CC = gcc
CFLAGS = -I $(INCPATH) -Wall -Wextra -pedantic -fPIC -O2
LDFLAGS = -shared
TARGET = libmy_malloc_$(HOSTTYPE).so
LINK_NAME = libmy_malloc.so
SRC = malloc.c internal.c
OBJ = $(SRC:.c=.o)
RM = rm -vf
LN = ln
all: $(TARGET)
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
$(LN) -s $(TARGET) $(LINK_NAME)
clean:
$(RM) $(OBJ)
fclean: clean
$(RM) $(TARGET) $(LINK_NAME)
re: fclean all
You can set all of your flag on the CFLAGS line!