According to the datasheet snippet above, TIM1 can be clocked by the internal clock (CK_INT). What is this internal clock? I have a feeling that it's just the APB1 Timer Clocks (Mhz) in the below clock tree, but is that correct? Why is it called an internal clock in the datasheet?
From the 48MHz limit I'm assuming it's an STM32F0 series MCU.
The clock tree is documented a few chapters back, in Reset and clock control (RCC) / Clocks.
Why is it called an internal clock in the datasheet?
Because it is, well... internal. As opposed to an external clock, which is coming from an external source.
Related
Thank you for visiting my question.
I'm now trying to set up my STM32 device(NUCLEO STM32F401RE) to use timer and found that which clock the timer is working based on.
TIM2 is used so the clock signal should come from APB1.
Bus info
Below is my clock configuration.
Clock config
Here I have some questions. There are two clocks: APB1 peripheral clocks and APB1 Timer clocks.
What's the difference of these? Why are these separated, one is prescaled and the other is not?
On which clock the TIM2 works based after all?
It can be the difference between peripheral's configuration registers, that you access via APB1 with APB1 speed, and the clock timer, that ticks the counter of the clock.
Here is a clock tree section of RCC peripheral of STM32F401 reference manual RM0368, page 94:
Page 95:
And right after that is yet another interesting piece:
The last piece talks about configuration that isn't often mentioned, I've usually seen it by default, but hey, you have quite a bit a flexibility here.
In default scenario, if APB clock is not equal to system clock (i.e. APB prescaler is greater than 1), then Timer counter clocks are doubled.
So if my MCU runs at 48MHz and APB1 is also 48MHz, I access timer's registers at 48MHz, and the timer (at timer prescaler=1) ticks at 48MHz.
But if my MCU runs at 84MHz, but my APB1 runs at 42MHz, then I access timer's registers at 42MHz, but the timer (at timer prescaler=1) ticks at 84MHz.
Very often, when your MCU is at max system clock frequency, APB bus will have a prescaler greater than one, meaning the timers' counters run at double their bus speed.
I am using TIM1 on a H743ZI with 3 PWM channels.
I am trying to maximize the PWM resolution so I need to maximize the clock speed on TIM1.
the datasheet (screenshot below) gives 120MHz and 240MHz values for Max interface clock and Max timer clock.
What is the difference between the 2? I have the clocks setup as shown below, with 120MHz on APB2's peripheral clocks and 240MHz on APB2's Timer clocks.
I need a 24KHz frequency on the PWM channels so I set the ARR to 4999 which confirms the H743 is using the 120MHz value (and not the 240MHz one).
Is it because the I am using the timer in a hardware related manner - hence the "peripheral clock"?
of course, my follow up question, would be whether or not I could use the HRTIM instead?
Every timer consists of the counter which is fed by the timer clock and the control unit which is responsible for interfacing with the bus (core and another peripherals) which is fed by the interface clock.
More general all peripherals have a digital control part. This part is fed by the bus clock (the bus the particular peripheral is connected to). Many peripherals have more than one clock - for example ADC where the digital controller form the bus clock, and the analogue part fed from another clock source.
I am trying to understand how timer on the internal clock works.
I've attached my CubeMX config below.
For now, I have set the main clock to 480 MHz which is the maximum for this STM32H743ZI chip.
I am using TIM 2 so I am looking at APB1.
there from the clock tree I see that it is currently so to 240 MHz for Timer Clocks, and 120 MHz for Peripheral Clocks.
My first question is that why is it using the 120MHz where it clearly says "240 MHz" for "timer clocks on APB1"? I have verified the frequency with an oscilloscope.
It is a long shot but according to what I read is that the maximum timer clock for this chip is 200 MHz. So 240 being greater than 200, perhaps the chip is automatically applying a /2 divider? I would think the clock configuration tree would say something, instead of allowing the "240 MHz" to be applied?
My second question:
For the sake argument, let's say that the maximum timer clock really is 200 MHz, how do I go about setting 200 MHz as clock frequency for APB1? I am sure there is no way to achieve 200 MHz without compromising on the max MCU clock and bring it down from 480 to 400 MHz perhaps?
Can I trust the automatic prescaler/multiplier adjustments that CubeMX is doing whenever I change something?
How did you checked it with the scope? It is inside the chip?
The timer clock is 240MHz, other peripheral clocks connected to the APB1 are 120MHz.
according to what I read is that the maximum timer clock for this chip
is 200 MHz.
Where did you read that? official documentation says something different
I think this question does not make too much sense
You see the values, you can check them manually if you wish, but in this case computers are usually are better than humans. Personally I did not have any problems with Cube. BTW I use it only for the clocks (I am too lazy to calculate all the prescallers by hand), but I program it bare register way.
I'm a bit lost with STM32L486 clock management.
I want to change the clock frequency at run-time. Typically I want to be in Low-Power Run/Sleep mode most of the time, and at full frequency the rest of the time.
I know how to set up SysClk either at 80MHz using PLL or at 1MHz using MSI for example.
However the problem is that changing Sysclk is messing up most peripherals setup. For example the USART is not working anymore if I change the clock.
Is it a common practice to do that ( changing the frequency at runtime ) ?
The peripherals I need to use are: LPTIM ( no problem since they can be clocked independantly from SysClk ), ADC, AES accelerator, USART, TIM, SPI.
On STM32L4xx it is not so hard, if you look on "Clock tree" figure in datasheet, many peripherals which are clock dependent (USART, LPTIM, I2C, ..) can be driven with other clock sources than BUS clock, there is also possible to use LSE or internal HSI.
Although internal HSI is not crystal controlled is from my experience enough accurate for UART, also in bigger range of temperatures, but you can tune frequency of this oscillator by comparing its frequency with an external and more accurate clock during runtime, or use auto-buadrate detection.
I am confused with the clock system on my STM32F7 device (Cortex-M7 microcontroller from STMicroelectronics). The reference manual does not clarify the differences between these clocks sufficiently:
SYSCLK
HCLK
FCLK
The reference manual reads in chapter << 5.2 Clocks >> "The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8."
This statement contradicts the figure from CubeMX. Notice that in CubeMX I can choose myself the prescaler from HCLK to 'Cortex System Timer'. It is not necessarily a division by 8.
Normally the only difference between HCLK and FCLK is that :
HCLK is the main CPU clock, also used for AHB interface. It can be gated when the CPU is sleeping (WFI for example)
FCLK is synchronous to HCLK but is not gated when the CPU goes to sleep, so that it can awake in case of interrupt.