I am confused with the clock system on my STM32F7 device (Cortex-M7 microcontroller from STMicroelectronics). The reference manual does not clarify the differences between these clocks sufficiently:
SYSCLK
HCLK
FCLK
The reference manual reads in chapter << 5.2 Clocks >> "The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8."
This statement contradicts the figure from CubeMX. Notice that in CubeMX I can choose myself the prescaler from HCLK to 'Cortex System Timer'. It is not necessarily a division by 8.
Normally the only difference between HCLK and FCLK is that :
HCLK is the main CPU clock, also used for AHB interface. It can be gated when the CPU is sleeping (WFI for example)
FCLK is synchronous to HCLK but is not gated when the CPU goes to sleep, so that it can awake in case of interrupt.
Related
Thank you for visiting my question.
I'm now trying to set up my STM32 device(NUCLEO STM32F401RE) to use timer and found that which clock the timer is working based on.
TIM2 is used so the clock signal should come from APB1.
Bus info
Below is my clock configuration.
Clock config
Here I have some questions. There are two clocks: APB1 peripheral clocks and APB1 Timer clocks.
What's the difference of these? Why are these separated, one is prescaled and the other is not?
On which clock the TIM2 works based after all?
It can be the difference between peripheral's configuration registers, that you access via APB1 with APB1 speed, and the clock timer, that ticks the counter of the clock.
Here is a clock tree section of RCC peripheral of STM32F401 reference manual RM0368, page 94:
Page 95:
And right after that is yet another interesting piece:
The last piece talks about configuration that isn't often mentioned, I've usually seen it by default, but hey, you have quite a bit a flexibility here.
In default scenario, if APB clock is not equal to system clock (i.e. APB prescaler is greater than 1), then Timer counter clocks are doubled.
So if my MCU runs at 48MHz and APB1 is also 48MHz, I access timer's registers at 48MHz, and the timer (at timer prescaler=1) ticks at 48MHz.
But if my MCU runs at 84MHz, but my APB1 runs at 42MHz, then I access timer's registers at 42MHz, but the timer (at timer prescaler=1) ticks at 84MHz.
Very often, when your MCU is at max system clock frequency, APB bus will have a prescaler greater than one, meaning the timers' counters run at double their bus speed.
I am using TIM1 on a H743ZI with 3 PWM channels.
I am trying to maximize the PWM resolution so I need to maximize the clock speed on TIM1.
the datasheet (screenshot below) gives 120MHz and 240MHz values for Max interface clock and Max timer clock.
What is the difference between the 2? I have the clocks setup as shown below, with 120MHz on APB2's peripheral clocks and 240MHz on APB2's Timer clocks.
I need a 24KHz frequency on the PWM channels so I set the ARR to 4999 which confirms the H743 is using the 120MHz value (and not the 240MHz one).
Is it because the I am using the timer in a hardware related manner - hence the "peripheral clock"?
of course, my follow up question, would be whether or not I could use the HRTIM instead?
Every timer consists of the counter which is fed by the timer clock and the control unit which is responsible for interfacing with the bus (core and another peripherals) which is fed by the interface clock.
More general all peripherals have a digital control part. This part is fed by the bus clock (the bus the particular peripheral is connected to). Many peripherals have more than one clock - for example ADC where the digital controller form the bus clock, and the analogue part fed from another clock source.
I had configured GPIO PR4 to work as external interrupt trigger on raising edge.but the interrupt ISR not trigger.same code worked well with GPIO PC5.My platform is Cortex M3 (TI F28M36x).
GPIO PC5 has same useage with PR4(different interrupt source)worked well.
I had check the external wave in PR4 (high level more than 3.0V).
I found PR4 use AHP bus,but PC5 use APB bus,I wonder is this difference make the different result?
My configure code like this:
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
GPIOPinTypeGPIOInput(GPIO_PORTR_BASE, GPIO_PIN_4);
GPIOPinIntClear(GPIO_PORTR_BASE,GPIO_PIN_4);
GPIOIntTypeSet(GPIO_PORTR_BASE, GPIO_PIN_4, GPIO_BOTH_EDGES);
IntRegister(INT_GPIOR, IntGPIORHandler);
IntEnable(INT_GPIOR);
GPIOPinIntEnable(GPIO_PORTR_BASE, GPIO_PIN_4);
ISR(IntGPIORHandler) never entered when debug in CCS tools.
I have found solution on TI community.It's not result in AHB problem but driverlib is too old.
https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/552983?tisearch=e2e-sitesearch&keymatch=GPIO%20port%20R%20interrupt
I use these code instead "IntRegister() and IntEnable()".
IntRegister(148, IntGPIORHandler);
HWREG(0xE000E110) = 1 << (132 - 128);
According to the datasheet snippet above, TIM1 can be clocked by the internal clock (CK_INT). What is this internal clock? I have a feeling that it's just the APB1 Timer Clocks (Mhz) in the below clock tree, but is that correct? Why is it called an internal clock in the datasheet?
From the 48MHz limit I'm assuming it's an STM32F0 series MCU.
The clock tree is documented a few chapters back, in Reset and clock control (RCC) / Clocks.
Why is it called an internal clock in the datasheet?
Because it is, well... internal. As opposed to an external clock, which is coming from an external source.
How can I increase the USART baud rate to 2Mbps, 3Mbps or 4Mbps. I am using STM32L151RCT6A, I am able to run to 921600. I have set clock with PLL 32MHz. On the datasheet it is given, which shows it is possible, Has anyone ever done this?
The datasheet only outlined the specific part and its peripheral set and electrical characteristics. For information on how to use the device you need the Reference Manual. This gives the following equation for baud rate:
Tx/Rx baud = CK_APB1 / (8 x (2 - OVER8) x USARTDIV)
Where USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
When OVER8=0, the fractional part is coded on 4 bits and programmed by the
DIV_fraction[3:0] bits in the USART_BRR register
When OVER8=1, the fractional part is coded on 3 bits and programmed by the
DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction3 must be kept
cleared.
The USARTs are on the APB1 bus, Figure 12 in the reference manual is the clock tree, which shows how the APB1 clock is derived from the PLL clock. The maximum APB1 clock is 32MHz. OVER8=1 is required for higher speeds, giving:
baud = 32X106 / (USARTDIV x 8).
So USARTDIV = 32X106 / (baud x 8)
For 4Mbps therefore, USARTDIV=1 (see table 138 S.No.12 for details). For 2Mps, USARTDIV=2. To achieve 3Mbps you will have to reduce the APB1 clock to 24MHz and set USARTDIV=1 (see table 131). But note that the clock rate changes for all other APB1 peripherals too.
The simplest way to correctly program the USART baud rate is via the STM32L1xx standard peripheral library. Also to determine the correct peripheral clock settings (and more), and generate initialisation code, you can use STM's MicroXplorer tool.