GNU make doesn't include headerfile - c

I have been searching for 6 hours and I can't seem to find the issue with this GNU make file, everytime I try to compile by main.o by the order
make main.o
it gives me this error:
arm-none-eabi-gcc -c main.c -mcpu=cortex-m4 -mthumb --
specs=nosys.specs -Wall -Werror -g -O0 -std=c99 -o main.o
main.c:23:22: fatal error: platform.h: No such file or directory
#include "platform.h"
^
compilation terminated.
Makefile:52: recipe for target 'main.o' failed
make: *** [main.o] Error 1
makefile:
include sources.mk
# Platform Overrides
PLATFORM = MSP432
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = thumb
SPECS = nosys.specs
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
TARGET = c1m1
LDFLAGS = -Wl,-Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS) -Wall -Werror -g -O0 -std=c99
CPPFLAGs =
.PHONY: all
all: $(TARGET).out
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
%.o : %.c
$(CC) -c $< $(CFLAGS) -o $#
OBJS = $(SOURCES:.c=.o)
$(TARGET).out: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
sources.mk:
# Add your Source files to this variable
SOURCES =./main.c \
./memory.c \
./startup_msp432p401r_gcc.c \
./system_msp432p401r.c \
./interrupts_msp432p401r_gcc.c
# Add your include paths to this variable
INCLUDES =-I./include/CMSIS \
-I./include/common \
-I./include/msp432
here's my code on github:
github repository

You have not used the INCLUDES macro in makefile's CFLAGS macro. Consequently the arm-none-eabi-gcc ... command line does not specify the include paths to the compiler (or strictly the pre-processor).
CFLAGS = -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS) $(INCLUDES) -Wall -Werror -g -O0 -std=c99
^^^^^^^^^^^

Related

Trouble with arm-none-eabi-gcc during compilation on Mac OS (M1)

Context:
I'm using a Mac OS Monterey (12.5.1) with M1 pro processor
The last version of Xcode is installed
I'm trying to build an image to used it inside a raspberry pi and trying to interact with a Piface LED screen.
With the PI OS, I load my own kernel (.img) in the config.txt
I'm trying to compile c with (gcc) arm-none-eabi by Makefile :
MAINFILE = a2p1
OBJS = lib/piface.o
OBJS += lib/rpi-gpio.o lib/rpi-armtimer.o lib/rpi-interrupts.o lib/rpi-systimer.o
OBJS += lib/startup.o lib/syscalls.o
OBJS += $(MAINFILE).o
ELF = $(MAINFILE).elf
MAIN = $(MAINFILE).img
CROSS = arm-none-eabi-
CC = $(CROSS)gcc
AS = $(CROSS)as
SIZE = $(CROSS)size
OCOPY = $(CROSS)objcopy
CFLAGS = -march=armv8-a+crc -mtune=cortex-a53 -mfpu=vfp -mfloat-abi=soft -ffunction-sections -fdata-sections -fno-common -g -std=gnu99 -Wall -Wextra -Os -Ilib -DRPI3=1 -DIOBPLUS=1
LFLAGS = -static -nostartfiles -lc -lgcc -specs=nano.specs -Wl,--gc-sections -lm
LSCRIPT = lib/rpi3.ld
LDFLAGS += -u _printf_float
.PHONY: all clean run
all: $(MAIN)
%.o: %.c
$(CC) $(CFLAGS) -c -o $# $^
$(ELF): $(OBJS)
$(CC) -T $(LSCRIPT) $(CFLAGS) $(LFLAGS) $(LDFLAGS) -o $# $^
$(SIZE) $#
$(MAIN): $(ELF)
$(OCOPY) $< -O binary $#
clean:
rm -f $(MAIN) $(ELF) $(OBJS)
run: $(MAIN)
I've installed arm-none-eabi-gcc using 'port' this way :
sudo port install arm-none-eabi-gcc
Here is my errors:
can not find -lc_nano : No such file or directory
/opt/local/lib/gcc/arm-none-eabi/12.2.0/../../../../arm-none-eabi/bin/ld
: can not find -lg_nano : No such file or directory
/opt/local/lib/gcc/arm-none-eabi/12.2.0/../../../../arm-none-eabi/bin/ld
: can not find -lc_nano : No such file or directory
How the error occur :
When the compiler is trying to run this (I suppose this is the linking step):
arm-none-eabi-gcc -T lib/rpi3.ld -march=armv8-a+crc -mtune=cortex-a53
-mfpu=vfp -mfloat-abi=soft -ffunction-sections -fdata-sections -fno-common -g -std=gnu99 -Wall -Wextra -Os -Ilib -DRPI3=1 -DIOBPLUS=1 -static -nostartfiles -lc -lgcc -specs=nano.specs -Wl,--gc-sections -lm -u _printf_float -o a2p1.elf lib/piface.o lib/rpi-gpio.o lib/rpi-armtimer.o lib/rpi-interrupts.o lib/rpi-systimer.o
lib/startup.o lib/syscalls.o a2p1.o
I got the same issue with the port, remove it and use instead :
brew install --cask gcc-arm-embedded
( https://formulae.brew.sh/cask/gcc-arm-embedded )

MAKEFILE,COMPILE,GCC and LINKING

I am getting this error while running make file to link the .o files.
command is $make build PLATFORM=HOST or $make build PLATFORM=MSP432,both gives the same error.
gcc main.o memory.o -DHOST -g -O0 -std=c99 -Wall -Werror -I../src/ -I../include/CMSIS/ -I../include/msp432/ -I../include/common/ -I../ -Wl,-Map=c1m2.map -L/usr/local/lib -T ../msp432p401r.lds -o c1m2.out
/usr/bin/ld: c1m2.out: Not enough room for program headers, try linking with -N
/usr/bin/ld: final link failed: Bad value
collect2: error: ld returned 1 exit status
Makefile:79: recipe for target 'c1m2.out' failed
make: *** [c1m2.out] Error 1
and my makefile script:
include sources.mk
# Platform Overrides
PLATFORM = HOST
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = armv7e-m
SPECS = nosys.specs
# Compiler Flags and Defines
# Conditional statements to choose the platform(host/msp432) else invalid platform message is diplayed.
ifeq ($(PLATFORM),HOST)
CC = gcc
CFLAGS = -DHOST
LD = ld
else
CC = arm-none-eabi-gcc
CFLAGS = -DMSP432 -mcpu=$(CPU) -march=$(ARCH) --specs=$(SPECS) -mfloat-abi=hard -mfpu=fpv4-sp-d16
LD = arm-none-eabi-ld
endif
TARGET = c1m2
LDFLAGS = -Wl,-Map=$(TARGET).map -T ../msp432p401r.lds
CPPFLAGS = -g -O0 -std=c99 -Wall -Werror $(INCLUDES)
OBJS = $(SRCS:.c=.o)
%.o : %.c
$(CC) -c $< $(CFLAGS) $(CPPFLAGS) -o $#
pre = $(SRCS:.c=.i)
%.i : %.c
$(CC) -c $< $(CFLAGS) $(CPPFLAGS) -E -o $#
asem =$(SRCS:.c=.asm):
%.asm : %.c
$(CC) -c $< $(CFLAGS) $(CPPFLAGS) -S -o $#
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
$(TARGET).out: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -o $#
.PHONY: clean
clean:
rm -f $(OBJS) $(pre) $(asem) $(TARGET).out $(TARGET).map
I have created this for running both in HOST and the given processor(MSP432),please don't bother poor formatting.

Makefile claims object file is up to date, but it does not exist

I have this makefile (I cut out the irrelevant parts):
CC = gcc
EXEC = mtm_cm
LIB = -L. -lmtm
DEBUG = -g
CFLAGS = -std=c99 -Wall -Werror -pedantic-errors -DNDEBUG $(DEBUG)
OBJS = command_parser.o course_manager.o grade_data.o student.o \
grade_sheet_data.o print_utilities.o semester.o string_utilities.o
$(EXEC): $(OBJS) main.o
$(CC) $(DEBUG) $(OBJS) main.o $(LIB) -o $#
... here the $(OBJS) targets are found ...
tests: $(OBJS) student_test grade_data_test
grade_data_test: tests/grade_data_test.o
$(CC) $(DEBUG) $(OBJS) tests/$#.o $(LIB) -o $#
student_test: tests/student_test.o
$(CC) $(DEBUG) $(OBJS) tests/$#.o $(LIB) -o $#
tests/student_test.o: tests/student_test.c tests/new_test_utilities.h \
student.h list.h grade_sheet_data.h
tests/grade_data_test.o: tests/grade_data_test.c tests/new_test_utilities.h \
grade_data.h grade_sheet_data.h list.h
Everything works normally, except the grade_data part.
That is, if I call make, the executable mtm_cm is created, and if I call make tests, then student_test is created, but not grade_data_test.
Instead, I get an error:
... former successful compilations ...
gcc -g command_parser.o course_manager.o grade_data.o student.o grade_sheet_data.o print_utilities.o semester.o string_utilities.o tests/grade_data_test.o -L. -lmtm -o grade_data_test
gcc: tests/grade_data_test.o: No such file or directory
But it did not merely skip the dependency of the target grade_data_test. Instead, let us run make tests/grade_data_test.o --debug=v, and get the output:
...
Finished prerequisites of target file `tests/grade_data_test.o'.
Must remake target `tests/grade_data_test.o'.
Successfully remade target file `tests/grade_data_test.o'.
make: `tests/grade_data_test.o' is up to date.
But the file does not exist.
The directories have enough permission, and I don't have directories with the same name as files.
Can you help me find out the solution?

makefile for creating (.so) file from existing files

I have 4 files: 1.c, 1.h, 2.c, 2.h.
I need a makefile, which will create a dynamic library (.so) from those 4 files.
I have tried to write a makefile like this:
library.so : 1.c 1.h 2.c 2.h
but it did not work. It would be great, if someone helps me, thanks.
Something like
CC=gcc
CFLAGS= -Wall -g -O -fPIC
RM= rm -f
.PHONY: all clean
all: library.so
clean:
$(RM) *.o *.so
library.so: 1.o 2.o
$(LINK.c) -shared $^ -o $#
1.o: 1.c 1.h 2.h
2.o: 2.c 1.h 2.h
But this is untested! I am assuming Linux with GNU make, and a directory containing only the source code of your library (with the above Makefile), which might be bad practice -you might want a test case- (you could have a special Makefile rule for %.pic.o depending on %.c, etc...)
Hints: use make -p to understand the builtin rules. Then make --trace or (with remake) remake -x to understand a bit more what make is doing.
Read also Drepper's paper: How to Write Shared Libraries, documentation of GNU make, Program Library HowTo, this answer, ...
The simplest way is:
CXXFLAGS += -fPIC
CXXFLAGS += -O3
x.so: 1.o 2.o
$(LINK.cc) -shared $^ $(LOADLIBS) $(LDLIBS) -o $#
Slightly more advanced:
CC = gcc
FLAGS = # -std=gnu99 -Iinclude
CFLAGS = -fPIC -g #-pedantic -Wall -Wextra -ggdb3
LDFLAGS = -shared
DEBUGFLAGS = -O0 -D _DEBUG
RELEASEFLAGS = -O2 -D NDEBUG -combine -fwhole-program
TARGET = example.so
SOURCES = $(wildcard *.c)
HEADERS = $(wildcard *.h)
OBJECTS = $(SOURCES:.c=.o)
all: $(TARGET)
$(TARGET): $(OBJECTS)
$(CC) $(FLAGS) $(CFLAGS) $(DEBUGFLAGS) -o $(TARGET) $(OBJECTS)
CC = gcc # C compiler
CFLAGS = -fPIC -Wall -Wextra -g # C flags
LDFLAGS = -shared # linking flags
RM = rm -f # rm command
TARGET_LIB = sh_main.so # target lib
SRCS = add.c sub.c main.c # source file
DEPS = header.h # header file
OBJS = $(SRCS:.c=.o) # object file
.PHONY: all
all: ${TARGET_LIB}
$(TARGET_LIB): $(OBJS)
$(CC) ${LDFLAGS} -o $# $^ # -o $# says, put the output of the compilation in the file named on the left side of the :
$(SRCS:.c=.d):%.d:%.c
$(CC) $(CFLAGS) -MM $< >$# # the $< is the first item in the dependencies list, and the CFLAGS macro is defined as above
include $(SRCS:.c=.d)
.PHONY: clean
clean:
-${RM} ${TARGET_LIB} ${OBJS} $(SRCS:.c=.d)
After the shared library created successfully. We need to install it.
Become the root user.
Copy the shared library into standard directory "/usr/lib".
Run ldcofig command.
Recompile your .c file with shared library.
root#Admin:~/C/SharedLibrary# gcc -c main.c
root#Admin:~/C/SharedLibrary# gcc -o main main.o sh_main.so
root#Admin:~/C/SharedLibrary# ldd main
Note: In my case.
main.c: main C file
sh_main.so: shared library.
I'm no gnu make expert, this seems reasonable to me
CFLAGS+=-fPIC
%.so: ; $(LINK.c) $(LDFLAGS) -shared $^ -o $#
library.so: 1.o 2.o # default target first
# changes to `1.h` imply `1.o` needs to be rebuilt
1.o: 1.h
2.o: 2.h

makefile compiling multiples targets

This is my first post in this forum. Sorry for bothering but I've been looking for something similar and strangely I couldn't find it. Here's the issue.
I have three (main) files with no headers and I want to compile them either at once (if I simply type "make") or one by one (if I specify the name of the file with no extension). So I built my makefile but something is wrong in the command
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
where I got this error
make: *** No rule to make target....
here's the complete file
.SUFFIXES: .c
ROOT = $(addprefix $(PWD), /)
BUILDS_DIR = $(addprefix $(ROOT), builds/)
SRCS_DIR = $(addprefix $(ROOT), src/)
SRCS = $(wildcard $(SRCS_DIR)*.c)
TARGETS = ${SRCS:$(SRCS_DIR)%.c=%}
EXES = ${addprefix $(BUILDS_DIR), $(TARGETS)}
CC = gcc
CFLAGS = -Wall -O3
RM = rm -f
.PHONY: all $(TARGETS) clean
all: $(TARGETS)
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) \
$< \
-o $#
#echo -e "\n\n\t\t*** Compile successfully! ***\n" ;
clean:
$(RM) $(EXES) \
$(SRCS_DIR)*~
#echo -e "\n\n\t\t*** Cleanup complete! ***\n"
Where am I wrong? I guess the answer is very silly and probably based on a basic error.
thanks in advance
Assuming GNU Make (since you use its syntax).
The, or the first, problem is that you are trying to rewrite the target static pattern incorrectly, by trying to concatenate the target directory to the pattern, rather than simply using the target's filename.
You had:
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $#
The solution is to use add the directory path on the command line
$(TARGETS): % : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $(BUILDS_DIR)$#
Lets assume that your three source files are file1.c, file2.c and file3.c. I would created the makefile to look like this (assuming GNU make)
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
file1 : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
file2 : file2.c
$(CC) $(CFLAGS) -c file2.c -o file2.o
file3 : file3.c
$(CC) $(CFLAGS) -c file3.c -o file3.o
clean :
$(RM) *.o $(PROG) *.*~
A sample using this make file is (I use the -n to show what rules would be run, but not actually run them because my source files are empty files for testing.)
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file1
gcc -ansi -Wall -pedantic -c file1.c -o file1.o
We can shorten the above make file my making use of wild-cards;
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
% : %.c
$(CC) $(CFLAGS) -c $< -o $#.o
clean :
$(RM) *.o $(PROG) .~
We need to append a '.o' to the output file name so that we are creating files in the format defined by the $(OBJ) variable of the first build rule works correctly. Doing this gives the following example runs:
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file2
gcc -ansi -Wall -pedantic -c file2.c -o file2.o
BTW, I personally don't mind typing an extra two characters and I like having my target match the output of the set of rules that get run, so I would write the rules as either
file1.o : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
or
%.o :%.c
$(CC) $(CFLAGS) -c $< -o $#
Finally I strongly suspect that when we execute make or make all, we are not running the file-specific rules in the lower part of the makefile, rather we are running the the built in rule described in the GNU manual as: "n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c".

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