Building linux kernel module - c

Im a windows driver programmer who is a complete newbie in linux kernel development.I have installed linux kernel headers. I am trying my helloworld module in linux kernel.
#include <linux/init.h>
#include <linux/module.h>
/*MODULE_LICENSE("Dual BSD/GPL");*/
static int hello_init(void)
{
printk(KERN_ALERT "Hello, world\n");
return 0;
}
static void hello_exit(void)
{
printk(KERN_ALERT "Goodbye, cruel world\n");
}
module_init(hello_init);
module_exit(hello_exit);
following is the code for my module. makefile for my build is
obj-m +=tryout.o
KDIR =/usr/src/linux-headers-4.13.0-37-generic
all:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o *.ko *.mod.* *.symvers *.order
but im getting
'fatal error: linux/init.h: No such file or directory while making this module'. What could be the possible reason? and how can i resolve it?

Your Makefile is mis-configured. In particular you used SUBDIRS whereas you're supposed to use M and your $(PWD) is meaningless, you should use pwd to be simple (or $$PWD); Here's how you should set it up:
ifneq ($(KERNELRELEASE),)
# kbuild part of makefile
obj-m := tryout.o
# any other c files that you would like to include go into
# yourmodule-y := <here> e.g.:
# tryout-y := tryout-1.o tryout-2.o
else
# normal makefile
KDIR ?= /usr/src/linux-headers-4.13.0-37-generic
# you really should set KDIR up as:
# KDIR := /lib/modules/`uname -r`/build
all::
$(MAKE) -C $(KDIR) M=`pwd` $#
# Any module specific targets go under here
#
endif
Configuring your makefile like this will allow you to simply type make in your module directory and it will invoke the Kernel's kbuild subsystem which will in-turn use the kbuild part of your Makefile.
Read up on https://www.kernel.org/doc/Documentation/kbuild/modules.txt for all the different permutations on how to do this. It comes with examples.

Related

.ko file not being built when building kernel modules

I am currently trying to learn how to make kernel modules from the 'Linux Device Drivers' book. I have the basic example typed out as follows:
#include <linux/init.h>
#include <linux/module.h>
MODULE_LICENSE("Dual BSD/GPL");
static int hello_init(void)
{
printk(KERN_ALERT "Hello, world\n");
return 0;
}
static void hello_exit(void)
{
printk("Goodbye, cruel world\n");
}
module_init(hello_init);
module_exit(hello_exit);
and I am using the following makefile to compile the file above, hello.c
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
When I run the make command, the console output is as follows:
make -C /lib/modules/5.13.0-40-generic/build M=/home/finlay/src/linux-drivers modules
make[1]: Entering directory '/usr/src/linux-headers-5.13.0-40-generic'
MODPOST /home/finlay/src/linux-drivers/Module.symvers
make[1]: Leaving directory '/usr/src/linux-headers-5.13.0-40-generic'
For some reason the only files which are created are the following:
.Module.symvers.cmd
.modules.order.cmd
Module.symvers
modules.order
None of the files created seems to specifically be about the hello.c file. What's very strange is that this same file was working initially to create the hello.ko file however it is no longer working. Any ideas as to why this is not working?
I have now found the solution, I removed some lines from the makefile as I believed them to be redundant as I thought that they were only used if you were directly invoking the makefile from the kernel build directory. The correct makefile is below.
ifneq ($(KERNELRELEASE),)
obj-m := hello.o
else
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif

Makefile for linux kernel module issue

I'm writing a kernel module which will be a driver for my chinese Arduino.
I've read many guides about it and Makefiles in them are completely different. Some of them just is not working. And I want to understand how and why:)
For example, I have a simple beginner's code:
#define MODULE
#define __KERNEL__
#include <module.h> // определения для модуля
#include <init.h> // module_init и module_exit
#include <kernel.h> // printk
MODULE_AUTHOR("...");
MODULE_DESCRIPTION("Test module for linux kernel");
int module_start()
{
printk("This is a test module startup message\n");
return 0;
}
void module_stop()
{
printk("Module is dead\n");
return;
}
module_init(module_start);
module_exit(module_stop);
And also I have a Makefile which I found in manual:
CC=gcc
MODFLAGS:= -O2 -Wall -DLINUX
module.o: module.c
$(CC) $(MODFLAGS) -c module.c
So, as I know, my system uses .ko files as a modules. This is the first problem. The second is that this makefile just doesn't work.
When I make, I'm getting the error "missing module.h". But I certainly installed headers. They are in /usr/src/linux-headers-(3.2.0-4-686-pae) and /usr/src/linux-headers-(3.2.0-4-common).
There is no module.h in *pae directory, but it is in *common directory(most of the files are there). So, I just can't compile it neither with gcc nor the makefile.
Thank you for the answers.
The "standard Makefile" for a module build is :
obj-m := hello-1.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o *.ko *.mod.* *.symvers *.order
( Creating hello-1.ko from hello-1.c )
The only headers used are the ones in /lib/modules/uname -r/build/include/.
And there is no ``module.h´´ : Please enter like #include <linux/module.h> ( or asm/module.h ).
I can't speak for the .ko module question. I'm not sure what the question really is.
But as for the missing separator error, this is a common Makefile problem. Commands(the $CC line below) in Makefiles must be preceeded with a tab.
To fix, simply add a TAB before your $(CC) line like so:
CC=gcc MODFLAGS:= -O2 -Wall -DLINUX
module.o: module.c
$(CC) $(MODFLAGS) -c module.c
/ \
|
|
TAB

error in generating .ko file for simple hello world module for linux kernel

I am a beginner in linux kernel development and trying to load a simple module in linux.
I have created an hello.c file, to be loaded as kernel module.
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("A Simple Hello World module");
static int __init hello_init(void)
{
printk(KERN_INFO "Hello world!\n");
return 0;
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Cleaning up module.\n");
}
module_init(hello_init);
module_exit(hello_cleanup);
this hello.c and the makefile both, I have kept in /home/linux/ directory.
makefile
obj-m +=hello.o
src= /usr/src/linux-headers-3.5.0-17-generic
all:
$(MAKE) -C $(src) SUBDIR-$(PWD) modules
clean:
rm -rf *.o *.ko
to generate .ko file, when I run the make command on terminal from the /home/linux directory , I get following error
h2o#h2o-Vostro-1015:~/linux$ make
make -C /usr/src/linux-headers-3.5.0-17-generic SUBDIR-/home/h2o/linux modules
make[1]: Entering directory `/usr/src/linux-headers-3.5.0-17-generic'
make[1]: *** No rule to make target `SUBDIR-/home/h2o/linux'. Stop.
make[1]: Leaving directory `/usr/src/linux-headers-3.5.0-17-generic'
make: *** [all] Error 2
kindly advise what am I missing or doing wrong..
Makefile
obj-m := hello.o # Module Name is hello.c
KDIR := /lib/modules/$(shell uname -r)/build
all: $(MAKE) -C $(KDIR) M=$(PWD) modules
clean: $(MAKE) -C $(KDIR) M=$(PWD) clean $(RM) Module.markers
modules.order
its not guaranteed that headers file will always be located in /usr/src directory, but it will surely be located in /lib/modules directory.
make sure that system has latest header files
to find out which header files to be present
run `
uname -r
on terminal, output will be like
3.5.0-17-generic
to install header files run
sudo apt-get install linux-headers-$(uname -r)
You have:
$(MAKE) -C $(src) SUBDIR-$(PWD) modules
But it seems like you want:
$(MAKE) -C $(src)/SUBDIR-$(PWD) modules
Or something along those lines; where does the source code live? You need to -C there.
Kernel build system is a bit complex. It would be good to read the kernel build process documentation. Which gives better understanding about, say,
Targets like --- modules / modules_install
Options like --- -C $KDIR / M=$PWD
Command Syntax ---
$ make -C <path_to_kernel_src> M=$PWD
$ make -C /lib/modules/uname -r/build M=$PWD
$ make -C /lib/modules/uname -r/build M=$PWD modules_install
Loadable module goals --- obj-m
etc...

Compiling a simple device driver code

I just started learning linux device driver. I just wrote a simple device driver code and tried compiling it but when ever i do a make i get the following error
make: Nothing to be done for `default'
Here is my device driver code.
#include <linux/module.h>
#include <linux/version.h>
#include <linux/kernel.h>
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Manoj");
MODULE_DESCRIPTION("My First Driver");
static int __init ofd_init ( void ) {
printk (KERN_INFO "ofd registered");
return 0;
}
static int __exit ofd_exit ( void ) {
printk (KERN_INFO "ofd unregistered");
return 0;
}
module_init ( ofd_init );
module _exit ( ofd_exit );
And my Makefile is like this
# If KERNELRELEASE is defined, we've been invoked from the
# kernel build system and can use its language.
ifneq ($(KERNELRELEASE),)
obj-m := hello.o
# Otherwise we were called directly from the command
# line; invoke the kernel build system.
else
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif
And in the path /lib/modules/3.2.0-58-generic-pae/build is also present.
can anyone please tell why this particular make file not working ?
obj-m:= hello.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
Before make -C press tab for space
The problem is in the make file.
Give a tab space before the command.
This is a general rule in writing a Makefile.
Change
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
to
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
For more information about the error refer this link.

Building a kernel module from several source files which one of them has the same name as the module

Is it possible to build a kernel module from several source files which one of them has the same name as the module?
For example:
I want to build "mymodule.ko" with the following source files:
mymodule.c
mymodule_func.c
This makefile doesn't work:
#Makefile
obj-m += mymodule.o
mymodule-objs := mymodule.o mymodule_func.o
thanks
I found a solution, I placed my source file in a sub folder:
Makefile
src/mymodule.c
src/mymodule_func.c
#Makefile
obj-m += mymodule.o
mymodule-objs := ./src/mymodule.o ./src/mymodule_func.o
all:
make -C $(KERNEL_PATH) M=$(PWD) modules
clean:
make -C $(KERNEL_PATH) M=$(PWD) clean
Proper way to fix in kernel make file would be as:
#
obj-m+= my_module.o
#append other source files except my_module.c which would be include by default
my_module-objs+= src1.o src2.o
As per my understanding it is not possible to have the module name and the source name to be the same. It would be better to provide module name as module.o and use the Makefile for compiling loadable kernel module as shown below,
Makefile
# If KERNELRELEASE is defined, we've been invoked from the
# kernel build system and can use its language.
ifneq ($(KERNELRELEASE),)
**obj-m := module.o
module-objs := mymodule.o mymodule_func.o**
# Otherwise we were called directly from the command
# line; invoke the kernel build system.
EXTRA_CFLAGS += -DDEBUG
else
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif
clean:
$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) clean
You can use TARGET to name your .ko file as I did in this example:
TARGET = can
KDIR = /lib/modules/3.1.10-1.16-desktop/build
PWD := $(shell pwd)
obj-m += $(TARGET).o
can-objs := can_core.o can_open.o can_select.o can_sysctl.o can_write.o \
can_close.o can_ioctl.o can_read.o can_util.o \
can_debug.o can_error.o \
can_async.o can_sim.o
default:
make -C $(KDIR) M=$(PWD) modules
So after the build I ended with a bunch of object files and can.ko
Another solution is create symlink to the file, say:
mymodule.c: ln -sf mymodule.c _mymodule.c
Now, use _mymodule.o as the object name:
mymodule-objs := _mymodule.o
If anyone has stumbled upon this issue while working with Xilinx SoCs and petalinux, note the generated .bb (bitbake) file. Apart from specifying object files in the Makefile:
modulename-objs+= src1.o src2.o
all files (including headers) must be listed in the modulename.bb file's SRC_URI variable.

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