Makefile for linux kernel module issue - c

Question

I'm writing a kernel module which will be a driver for my chinese Arduino.
I've read many guides about it and Makefiles in them are completely different. Some of them just is not working. And I want to understand how and why:)
For example, I have a simple beginner's code:
#define MODULE
#define __KERNEL__
#include <module.h> // определения для модуля
#include <init.h> // module_init и module_exit
#include <kernel.h> // printk
MODULE_AUTHOR("...");
MODULE_DESCRIPTION("Test module for linux kernel");
int module_start()
{
printk("This is a test module startup message\n");
return 0;
}
void module_stop()
{
printk("Module is dead\n");
return;
}
module_init(module_start);
module_exit(module_stop);
And also I have a Makefile which I found in manual:
CC=gcc
MODFLAGS:= -O2 -Wall -DLINUX
module.o: module.c
$(CC) $(MODFLAGS) -c module.c
So, as I know, my system uses .ko files as a modules. This is the first problem. The second is that this makefile just doesn't work.
When I make, I'm getting the error "missing module.h". But I certainly installed headers. They are in /usr/src/linux-headers-(3.2.0-4-686-pae) and /usr/src/linux-headers-(3.2.0-4-common).
There is no module.h in *pae directory, but it is in *common directory(most of the files are there). So, I just can't compile it neither with gcc nor the makefile.
Thank you for the answers.

Answer 1

The "standard Makefile" for a module build is :
obj-m := hello-1.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o *.ko *.mod.* *.symvers *.order
( Creating hello-1.ko from hello-1.c )
The only headers used are the ones in /lib/modules/uname -r/build/include/.
And there is no ``module.h´´ : Please enter like #include <linux/module.h> ( or asm/module.h ).

Answer 2

I can't speak for the .ko module question. I'm not sure what the question really is.
But as for the missing separator error, this is a common Makefile problem. Commands(the $CC line below) in Makefiles must be preceeded with a tab.
To fix, simply add a TAB before your $(CC) line like so:
CC=gcc MODFLAGS:= -O2 -Wall -DLINUX
module.o: module.c
$(CC) $(MODFLAGS) -c module.c
/ \
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TAB