Linking Opencv libraries in C - c

I've been attempting to write test a simple program using the opencv library. I have the following test code I found on a tutorial. I am running OSX 10.9.2 and managed (I think) to successfully install opencv on my computer using homebrew. My problem is that I cannot get this code to compile because my make file throws errors anytime I try to compile. I believe the issue is that I have not properly linked the libraries, and no amount of googling seems to have helped me solve my problem.
////////////////////////////////////////////////////////////////////////
//
// This is a simple, introductory OpenCV program. The program reads an
// image from a file, inverts it, and displays the result.
//
////////////////////////////////////////////////////////////////////////
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cv.h>
#include <highgui.h>
int main(int argc, char** argv)
{
IplImage* img = cvLoadImage( "Conumdrum.jpeg", 0 ); //change the name (image.jpg) according to your Image filename.
cvNamedWindow( "Example1", CV_WINDOW_AUTOSIZE );
cvShowImage("Example1", img);
cvWaitKey(0);
cvReleaseImage( &img );
cvDestroyWindow( "Example1" );
return 0;
}
I found a sample makefile online that I've attempted to modify but to no avail, here is my makefile below:
# define the C compiler to use
CC = gcc
# define any compile-time flags
CFLAGS = -Wall -g
# define any directories containing header files other than /usr/include
#
INCLUDES = -I/Users/MY_NAME/Projects/Tank\ Game/Webcam_Tests/Webcam_Test_v1/include
# define library paths in addition to /usr/lib
# if I wanted to include libraries not in /usr/lib I'd specify
# their path using -Lpath, something like:
LFLAGS = -L/Users/MY_NAME/Projects/Tank\ Game/Webcam_Tests/Webcam_Test_v1/lib
# define any libraries to link into executable:
# if I want to link in libraries (libx.so or libx.a) I use the -llibname
# option, something like (this will link in libmylib.so and libm.so:
LIBS = -l libopencv_core.dylib -lm
# define the C source files
SRCS = Webcam_Test_v1.c
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
# Below we are replacing the suffix .c of all words in the macro SRCS
# with the .o suffix
#
OBJS = $(SRCS:.c=.o)
# define the executable file
MAIN = mycc
#
# The following part of the makefile is generic; it can be used to
# build any executable just by changing the definitions above and by
# deleting dependencies appended to the file from 'make depend'
#
.PHONY: depend clean
all: $(MAIN)
#echo Simple compiler named mycc has been compiled
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
# this is a suffix replacement rule for building .o's from .c's
# it uses automatic variables $<: the name of the prerequisite of
# the rule(a .c file) and $#: the name of the target of the rule (a .o file)
# (see the gnu make manual section about automatic variables)
.c.o:
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
clean:
$(RM) *.o *~ $(MAIN)
depend: $(SRCS)
makedepend $(INCLUDES) $^
# DO NOT DELETE THIS LINE -- make depend needs it
Terminal gives me the following output when I try to compile:
gcc -Wall -g -I/Users/MY_NAME/Projects/Tank\ Game/Webcam_Tests/Webcam_Test_v1/include -c Webcam_Test_v1.c -o Webcam_Test_v1.o
gcc -Wall -g -I/Users/MY_NAME/Projects/Tank\ Game/Webcam_Tests/Webcam_Test_v1/include -o mycc Webcam_Test_v1.o -L/Users/MY_NAME/Projects/Tank\ Game/Webcam_Tests/Webcam_Test_v1/lib -l libopencv_core.dylib -lm
ld: library not found for -llibopencv_core.dylib
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [mycc] Error
Any help would be much appreciated, I've been beating my head against a wall for a couple of days now trying to solve this issue. It should also be noted that I am a novice, especially when it comes to makefiles. Thanks.

Your linker option is wrong. Try with -lopencv_core instead of -l libopencv_core.dylib.
For example, if you want to link a library which filename is libfoo.dylib, the right linker option is -lfoo.
And you will need to add -lopencv_highgui too.

Related

undefined reference to 'pow' using makefile

I'm trying to use the pow function but the make command gives me this error. I did #include<math.h> at the start of the file.
Compiling the .c file on its own using gcc test.c -o test -lm works fine, but as part of my assignment, I have to use the makefile my instructors gave me. (What I'm guessing to be) its most relevant portion looks like this:
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
What should I try, and can I fix this without changing the contents of the makefile? Thank you.
Edit:
Including all of my code would be a mess, but this is what causes the error:
int max = pow(2, n);
(n is an int)
full makefile:
###############################################
# Makefile for compiling the program skeleton
# 'make' build executable file 'PROJ'
# 'make doxy' build project manual in doxygen
# 'make all' build project + manual
# 'make clean' removes all .o, executable and doxy log
###############################################
PROJ = proj # the name of the project
CC = gcc # name of compiler
DOXYGEN = doxygen # name of doxygen binary
# define any compile-time flags
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
###############################################
# You don't need to edit anything below this line
###############################################
# list of object files
# The following includes all of them!
C_FILES := $(wildcard *.c)
OBJS := $(patsubst %.c, %.o, $(C_FILES))
# To create the executable file we need the individual
# object files
$(PROJ): $(OBJS)
$(CC) $(LFLAGS) -g -o $(PROJ) $(OBJS)
# To create each individual object file we need to
# compile these files using the following general
# purpose macro
.c.o:
$(CC) $(CFLAGS) -g -c $<
# there is a TAB for each identation.
# To make all (program + manual) "make all"
all :
make
make doxy
# To make all (program + manual) "make doxy"
doxy:
$(DOXYGEN) *.conf &> doxygen.log
# To clean .o files: "make clean"
clean:
rm -rf *.o doxygen.log html

How to generate dependency files when generating object files of c sources with make

I am implementing a build system using the GNU tools, GCC and make to compile multiple targets, link them together and create a final executable. All these support two platforms; the host environment and the embedded system MSP432.
I am taking an introductory course on embedded systems and doing an assignment that I am fighting with some days ago. I was trying by myself reading over the internet, also reading here in stackoverflow but I don’t get it yet, I am still a rookie on this, so I hope someone can explain me or giving me a hint about how to fix the issue
As said, the build system must support the two platforms so at first step, I focus on making sure all works for the host environment.
In the makefile I have created rules for the following targets:
build - Generates executable file, object files, dependency files and map file
%.o: %.c ... - Generates object files and its dependencies
compile-all - Compiles all objects but do not link them
%.i: %.c - Generates preprocessed output of C source files
%.asm: %.C - Generates assembly output of C source files
clean - Clean all generated files
The issue is when executing make build PLATFORM=HOST
Running the command, we get:
.../src$ sudo make build PLATFORM=HOST
gcc -Wall -Werror -g -std=c99 -DHOST -Wl,-O0,-Map=c1m2.map main.c memory.c -I../includes/common -o c1m2.out
make: *** No rule to make target 'main.o', needed by 'build'. Stop.
I notice that the error comes because the line 132 were we have
%.o: %.c
This line is intended for disabling the built-in rule and using the user defined one that comes next line, but it is not doing it, so I try commenting this line and executing the build again and we get:
.../src$ sudo make build PLATFORM=HOST
gcc -Wall -Werror -g -std=c99 -DHOST -Wl,-O0,-Map=c1m2.map main.c memory.c -I../includes/common -o c1m2.out
gcc -Wall -Werror -g -std=c99 -DHOST -E -c -o main.o main.c
main.c:23:22: fatal error: platform.h: No such file or directory
compilation terminated.
< builtin >: recipe for target 'main.o' failed
make: *** [main.o] Error 1
Now it says that it does not find “platform.h” despite it being indicated by the INCLUDES variable that contains the location of the header file. Also, it is using the built-in recipe for generating the object files and fails.
So I am stuck at this point, the idea is building the output executable, the map file, the object files and its dependencies files when executing “make build PLATFORM=HOST”.
At the beginning I wrote the build target just for generating the output, the map and object files and did work and then after doing the modifications for generating the dependency files I got lost with this error.
The other recipes for generating preproceessed files, assembly files and doing a clean were working ok.
You can clone the folder with all the needed files from: https://github.com/Fornaso/C1M2.git
Thank you all in advance.
Here is my Makefile:
#******************************************************************************
# Copyright (C) 2017 by Alex Fosdick - University of Colorado
#
# Redistribution, modification or use of this software in source or binary
# forms is permitted as long as the files maintain this copyright. Users are
# permitted to modify this and use it to learn about the field of embedded
# software. Alex Fosdick and the University of Colorado are not liable for any
# misuse of this material.
#
#******************************************************************************
# Modified on April 2020 by Adrián Fornaso
#------------------------------------------------------------------------------
# Simple Makefile for multitarget build system
#
# Use: make [TARGET] [PLATFORM-OVERRIDES]
#
# Build Targets:
#
# build - Builds and links all source files and genereates:
#
# c1m2.map - Map file for the full build
# *.d - Dependency Files for each source file
# *.o - Individual object files
# c1m2.out - Output Executable file
#
#<FILE>.i - Builds <FILE>.i preprocessed file.
#<FILE>.asm - Builds <FILE>.i assembly file.
#<FILE>.o - Builds <FILE>.o object file.
#compile-all - Compile all objects but do NOT link them.
#clean - Removes all generated files.
#
# Platform Overrides: Conditionally assign the appropriate compiler flags,
# linker flags, and architecture flags. The target platform
# must be provided at the command line with the make
# command to set the platform you are compiling for.
#
# PLATFORM = MSP432 - The target embedded system will use
# the cross compiler, arm-none-eabi-gcc.
# PLATFORM = HOST - The host embedded system will use the
# native compiler, gcc.
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
#General Flags (Both Platforms)
#
# -Wall Enable All Warning Messages (CFLAGS)
# -Werror Treats All Warnings as Errors(CFLAGS)
# -g Generate Debugging Info in Executable (CFLAGS)
# -O0 The level of optimization (-O0, -O1, -O2, -O3)) (LDFLAGS)
# -std=c99 The C standard set (CFLAGS)
#
#------------------------------------------------------------------------------
#Target name
BASENAME = c1m2
TARGET = $(BASENAME).out
#General Flags
COMMONCFLAGS = -Wall -Werror -g -std=c99
COMMONLDFLAGS = -Wl,-O0,-Map=$(BASENAME).map
#No spaces after commas after -Wl option.
CPPFLAGS = -E
# -E flag makes the compiler stop in the preprocessed output
#Compile time switches
ifeq ($(PLATFORM), MSP432)
INCLUDES = -I../includes/common \
-I../includes/msp432 \
-I../includes/CMSIS
SOURCES = main.c \
memory.c \
interrupts_msp432p401r_gcc.c \
startup_msp432p401r_gcc.c \
system_msp432p401r.c
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = armv7e-m
SPECS = nosys.specs
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
LDFLAGS = $(COMMONLDFLAGS), -T=$(LINKER_FILE)
CFLAGS = $(COMMONCFLAGS) -D$(PLATFORM) -mcpu=$(CPU) \
-march=$(ARCH) --specs=$(SPECS)
OBJDUMP = arm-none-eabi-objdump
endif
ifeq ($(PLATFORM), HOST)
INCLUDES = -I../includes/common
SOURCES = main.c \
memory.c
CC = gcc
LD = ld
LDFLAGS = $(COMMONLDFLAGS)
CFLAGS = $(COMMONCFLAGS) -D$(PLATFORM)
OBJDUMP = objdump
endif
#Listing object files:
OBJECTS = $(SOURCES:.c=.o)
# 1. --------------------------------------------------------------------------
# Complete build: c1m2.map - Map file for the full build
# *.d - Dependency Files for each source file
# *.o - Individual object files
# c1m2.out - Output Executable file
# LDFLAGS contains the flags for creating the *.map file
.PHONY: build
build: $(TARGET) $(OBJECTS)
$(TARGET):
$(CC) $(CFLAGS) $(LDFLAGS) $(SOURCES) $(INCLUDES) -o $#
# 2. --------------------------------------------------------------------------
# //// Generates the object files of all c-program implementation files and its
# dependecies. ///////////////////////////////////////////////////////////
#This implementation places dependency files into a subdirectory named .deps.
DEPDIR := .deps
DEPFLAGS = -MT $# -MD -MP -MF $(DEPDIR)/$*.d
# Delete the built-in rules for building object files from .c files, so that
# our rule is used instead.
#%.o: %.c
# Our rule for building object files with its dependency
%.o: %.c $(DEPDIR)/%.d | $(DEPDIR)
$(CC) $(DEPFLAGS) -c $(CFLAGS) $(INCLUDES) -o $# $^
# Declare a rule for creating the dependency directory if it doesn’t exist.
$(DEPDIR): ; #mkdir -p $#
# Generate a list of all the dependency files that could exist.
DEPFILES := $(SRCS:%.c=$(DEPDIR)/%.d)
# Mention each dependency file as a target, so that make won’t fail if the file
# doesn’t exist.
$(DEPFILES):
# 2 bis. ----------------------------------------------------------------------
# /// Generates the object file of all c-program implementation files. ////////
#%.o: %.c
# $(CC) -c $(CFLAGS) $(INCLUDES) -o $# $^
# 3. --------------------------------------------------------------------------
# /// Compile all objects but do NOT link them. ///////////////////////////////
.PHONY: compile-all
compile-all: $(SOURCES)
$(CC) -c $(CFLAGS) $(INCLUDES) $^
# 4. --------------------------------------------------------------------------
# /// Generates the preprocessed output of all c-program implementation files.
%.i: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(INCLUDES) -o $# $^
# 5. --------------------------------------------------------------------------
# /// Create assembler file of a C source. ////////////////////////////////////
%.asm: %.c
$(CC) -S $(CFLAGS) $(INCLUDES) $< -o $#
# -S flag tells the compiler just generate the assembly file
# 6. --------------------------------------------------------------------------
# /// Removes all compiled objects, preprocessed outputs, assembly outputs,
# executable files and build output files. ////////////////////////////////
.PHONY: clean
clean:
rm -f $(OBJECTS) $(TARGET) $(BASENAME).map *.asm *.i
rm -r .dep
#End of file
There are two small mistakes which took me quite a while to see:
DEPFILES := $(SRCS:%.c=$(DEPDIR)/%.d) has to be DEPFILES := $(SOURCES:%.c=$(DEPDIR)/%.d) - otherwise DEPFILES is empty since SRCS is undefined.
In $(CC) $(DEPFLAGS) -c $(CFLAGS) $(INCLUDES) -o $# $^ the $^ (all the prerequisites) expands to e. g. main.c .deps/main.d, so a not yet existing .deps/main.d is passed as an input file; we want $*.c instead of $^.
Another minor error is:
rm -r .dep should be rm -r .deps or rm -r $(DEPDIR).

How can I compile a header file and a C file together?

I created a file.h and a file.c how can I compile them on Ubuntu?
You only need to compile your .c file(s), not your .h file(s).
To compile file.c on Ubuntu, you can use GCC:
gcc file.c -o my_program
...or Clang:
clang file.c -o my_program
It is possible to precompile your header files, but you only need precompiled headers in particular cases. More information here.
If file.h is not in the same folder as file.c, you can use GCC or Clang's -I option.
Example if file.h is in the include/ folder:
gcc -I include/ file.c -o my_program
In file.c you still have this instruction, with only the filename:
#include "file.h"
You can also use a more generic approach by the usage of a makefile.
Here is a short example of such a file:
# Declaration of variables
CC = gcc
CC_FLAGS = -w -Werror -Wall
# File names
# "prgoram" will be the name of the output produced from the make process
EXEC = program
#Incorporates all the files with .c extension
SOURCES = $(wildcard *.c)
OBJECTS = $(SOURCES:.c=.o)
# Main target
$(EXEC): $(OBJECTS)
$(CC) $(OBJECTS) -o $(EXEC)
# To obtain object files
%.o: %.c
$(CC) -c $(CC_FLAGS) $< -o $#
# To remove generated files
clean:
rm -f $(EXEC) $(OBJECTS)
To use this utility just make sure that the file itself is within the directory containing your source files and its name is either "makefile" or "Makefile".
To compile the code simply run the following command from your working directory:
make program
This command will automatically link all the source files within your working directory into one executable file with the name of "program". To run the program itself just use the command:
./program
To clean your project and the created executable you can run the command:
make clean
The makefile is very powerful when dealing with larger projects that contain a larger number of source files. Here you can check for more guidance on how to use makefiles. This is also a very detailed tutorial on the topic.
Use following command to compile your program(For GCC Compiler):
gcc file.c -o file
No need to compile file.h file.

New to c, linking error when using a method declared in a header that's included

I'm new to c and I'm trying to use a method from tester in my main.c class.
So here is main.c:
#include <stdbool.h>
#include <stdio.h>
#include "tester.h"
int main(void) {
bool is_valid = isTrue();
}
Here is tester.h:
#include <stdbool.h>
bool isTrue();
Here is tester.c:
#include "tester.h"
bool isTrue() {
return true;
}
And here is what happens when I try to compile:
$ make main tester
gcc -g -O0 -Wall --std=c99 -pedantic -g -O0 main.c -o main
main.c: In function ‘main’:
main.c:7:10: warning: unused variable ‘is_valid’ [-Wunused-variable]
bool is_valid = isTrue();
^
/tmp/ccwIzgJQ.o: In function `main':
/home/paul/CS261/p1-check/mess/main.c:7: undefined reference to `isTrue'
collect2: error: ld returned 1 exit status
make: *** [main] Error 1
My Makefile was provided by my professor. I can post the contents here, but I'm confident it's correct. I know there's a linking error happening here, but why? I included the tester.h file in my main.c, so shouldn't isTrue be defined? Assistance would be greatly appreciated.
Edit: Here is the Makefile:
# Simple Makefile
#
#
# This makefile builds a simple application that contains a main module
# (specified by the EXE variable) and a predefined list of additional modules
# (specified by the MODS variable). If there are any external library
# dependencies (e.g., the math library, "-lm"), list them in the LIBS variable.
# If there are any precompiled object files, list them in the OBJS variable.
#
# By default, this makefile will build the project with debugging symbols and
# without optimization. To change this, edit or remove the "-g" and "-O0"
# options in CFLAGS and LDFLAGS accordingly.
#
# By default, this makefile build the application using the GNU C compiler,
# adhering to the C99 standard with all warnings enabled.
# application-specific settings and run target
EXE=y86
MODS=p1-check.o
OBJS=
LIBS=
default: $(EXE)
test: $(EXE)
make -C tests test
# compiler/linker settings
CC=gcc
CFLAGS=-g -O0 -Wall --std=c99 -pedantic
LDFLAGS=-g -O0
# build targets
$(EXE): main.o $(MODS) $(OBJS)
$(CC) $(LDFLAGS) -o $(EXE) $^ $(LIBS)
%.o: %.c
$(CC) -c $(CFLAGS) $<
clean:
rm -f $(EXE) main.o $(MODS)
make -C tests clean
.PHONY: default clean
Am I missing a part of the command when I try to use the Makefile for linking? It's probably something on my end, but I'm not sure what.
I figured out what I was doing wrong. I should have been saying make main.o when I wanted to link files with it. I wasn't paying enough attention to the build commands in Makefile, it seems. Thanks to kaylum for the clarification between declarations and definitions.

custom igraph igraph_get_shortest_paths_dijkstra function on Mac OS X

To make a custom version of the function igraph_get_shortest_paths_dijkstra I made a copy of it from the file:structural_properties.c. I've yanked it out and put it in my local .c file and one of the modifications to my Makefile is the following, but I get an error:
gcc -I/usr/local/include/igraph -I/Users/saguinag/ToolSet/igraph-0.7.1/src -I/Users/saguinag/ToolSet/igraph-0.7.1 -o mycc comp_catpath.o -L/usr/local/lib -ligraph
Undefined symbols for architecture x86_64:
"_saguinag_get_shortest_path", referenced from:
_main in comp_catpath.o
ld: symbol(s) not found for architecture x86_64
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [mycc] Error 1
Where my Makefile starts out as:
## Author: Sal Aguinaga (c) 2015
CC=gcc
INCLUDES=-I/usr/local/include/igraph \
-I/Users/saguinag/ToolSet/igraph-0.7.1/src \
-I/Users/saguinag/ToolSet/igraph-0.7.1
LFLAGS=-L/usr/local/lib
LIBS=-ligraph
OUT=comp_catpath
OBJS=comp_catpath.o
# define the C source files
SRCS = comp_catpath.c
OBJS = $(SRCS:.c=.o)
# define the executable file
MAIN = mycc
.PHONY: depend clean
all: $(MAIN)
#echo Simple compiler named mycc has been compiled
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
# this is a suffix replacement rule for building .o's from .c's
# # it uses automatic variables $<: the name of the prerequisite of
# # the rule(a .c file) and $#: the name of the target of the rule (a .o file)
# # (see the gnu make manual section about automatic variables)
.c.o:
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
#
clean:
$(RM) *.o *~ $(MAIN)
#
depend: $(SRCS)
makedepend $(INCLUDES) $^
#
# DO NOT DELETE THIS LINE -- make depend needs it
do I need to specify the architecture? My machine is a MacBook Pro. When I type make -v I get that it's GNU Make 3.81 with the last line saying "This program built for i386-apple-darwin11.3.0" Is there a better way to do this?
You are compiling and linking a single source file, comp_catpath.c. In this file, you have defined the function main, and in main you try to call the function saguinag_get_shortest_path. However, you haven't defined the function saguinag_get_shortest_path in comp_catpath.c and it's also not defined in the igraph library or in the C standard library.
If you already put the definition of saguinag_get_shortest_path in another .c file, you need to include that file's name in the definition of SRCS in your Makefile. If you didn't define saguinag_get_shortest_path anywhere, you need to write a definition for it, either in comp_catpath.c or in a new file (that you then add to SRCS).

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