I'm trying to use the pow function but the make command gives me this error. I did #include<math.h> at the start of the file.
Compiling the .c file on its own using gcc test.c -o test -lm works fine, but as part of my assignment, I have to use the makefile my instructors gave me. (What I'm guessing to be) its most relevant portion looks like this:
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
What should I try, and can I fix this without changing the contents of the makefile? Thank you.
Edit:
Including all of my code would be a mess, but this is what causes the error:
int max = pow(2, n);
(n is an int)
full makefile:
###############################################
# Makefile for compiling the program skeleton
# 'make' build executable file 'PROJ'
# 'make doxy' build project manual in doxygen
# 'make all' build project + manual
# 'make clean' removes all .o, executable and doxy log
###############################################
PROJ = proj # the name of the project
CC = gcc # name of compiler
DOXYGEN = doxygen # name of doxygen binary
# define any compile-time flags
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
###############################################
# You don't need to edit anything below this line
###############################################
# list of object files
# The following includes all of them!
C_FILES := $(wildcard *.c)
OBJS := $(patsubst %.c, %.o, $(C_FILES))
# To create the executable file we need the individual
# object files
$(PROJ): $(OBJS)
$(CC) $(LFLAGS) -g -o $(PROJ) $(OBJS)
# To create each individual object file we need to
# compile these files using the following general
# purpose macro
.c.o:
$(CC) $(CFLAGS) -g -c $<
# there is a TAB for each identation.
# To make all (program + manual) "make all"
all :
make
make doxy
# To make all (program + manual) "make doxy"
doxy:
$(DOXYGEN) *.conf &> doxygen.log
# To clean .o files: "make clean"
clean:
rm -rf *.o doxygen.log html
Related
When trying to compile my c code I keep getting basic.c:5:10: fatal error: 'fftw3.h' file not found. I am compiling my c code using MacOS terminal and have Xcode installed.
I'm trying to write some c code which uses the fftw-3 library. fftw-3 has been installed using sudo port install fftw-3 and I have entered port contents fftw-3 which returned:
/opt/local/include/dfftw.h
/opt/local/include/dfftw_threads.h
/opt/local/include/drfftw.h
/opt/local/include/drfftw_threads.h
/opt/local/include/fftw_f77.i
/opt/local/lib/libdfftw.2.dylib
/opt/local/lib/libdfftw.a
/opt/local/lib/libdfftw.dylib
/opt/local/lib/libdfftw_threads.2.dylib
/opt/local/lib/libdfftw_threads.a
/opt/local/lib/libdfftw_threads.dylib
/opt/local/lib/libdrfftw.2.dylib
/opt/local/lib/libdrfftw.a
/opt/local/lib/libdrfftw.dylib
/opt/local/lib/libdrfftw_threads.2.dylib
/opt/local/lib/libdrfftw_threads.a
/opt/local/lib/libdrfftw_threads.dylib
/opt/local/share/info/fftw.info
/opt/local/share/info/fftw.info-1
/opt/local/share/info/fftw.info-2
/opt/local/share/info/fftw.info-3
/opt/local/share/info/fftw.info-4
/opt/local/share/info/fftw.info-5
I have been using a makefile and am trying to work out what needs including in it. At the moment I have:
# define the name of your source file(s)
SRCS = basic.c
# define the name of the object files(s) - we can do this automatically
OBJS = $(SRCS:.c=.o)
# tell MAKE which compiler to use
CCOMP = gcc
# flags for the compiler
# don't forget the -O3
CFLAGS = -Wall -O3 -fstrict-aliasing -Iinclude
#CFLAGS = -c -Wall -Iinclude
# flags for the linker. note -lm for the math library
LDFLAGS = -O3 -lm -L/opt/lib -I/opt/lib -L/opt/local/include -I/opt/lib
# the name of your executable file (the target) - here we put it in the top directory
TARGET = basic
# actions
all: $(OBJS)
$(CCOMP) -o $(TARGET) $(OBJS) $(LDFLAGS)
%.o: %.c
$(CCOMP) -c -o $# $< $(CFLAGS)
# delete all objects and target
clean:
rm -f $(OBJS) $(TARGET)
I'm not sure if the #CFLAGS and #LDFLAGS sections are correct? I would appreciate troubleshooting and any advice on what I need to do to get this working. Thanks!
I am implementing a build system using the GNU tools, GCC and make to compile multiple targets, link them together and create a final executable. All these support two platforms; the host environment and the embedded system MSP432.
I am taking an introductory course on embedded systems and doing an assignment that I am fighting with some days ago. I was trying by myself reading over the internet, also reading here in stackoverflow but I don’t get it yet, I am still a rookie on this, so I hope someone can explain me or giving me a hint about how to fix the issue
As said, the build system must support the two platforms so at first step, I focus on making sure all works for the host environment.
In the makefile I have created rules for the following targets:
build - Generates executable file, object files, dependency files and map file
%.o: %.c ... - Generates object files and its dependencies
compile-all - Compiles all objects but do not link them
%.i: %.c - Generates preprocessed output of C source files
%.asm: %.C - Generates assembly output of C source files
clean - Clean all generated files
The issue is when executing make build PLATFORM=HOST
Running the command, we get:
.../src$ sudo make build PLATFORM=HOST
gcc -Wall -Werror -g -std=c99 -DHOST -Wl,-O0,-Map=c1m2.map main.c memory.c -I../includes/common -o c1m2.out
make: *** No rule to make target 'main.o', needed by 'build'. Stop.
I notice that the error comes because the line 132 were we have
%.o: %.c
This line is intended for disabling the built-in rule and using the user defined one that comes next line, but it is not doing it, so I try commenting this line and executing the build again and we get:
.../src$ sudo make build PLATFORM=HOST
gcc -Wall -Werror -g -std=c99 -DHOST -Wl,-O0,-Map=c1m2.map main.c memory.c -I../includes/common -o c1m2.out
gcc -Wall -Werror -g -std=c99 -DHOST -E -c -o main.o main.c
main.c:23:22: fatal error: platform.h: No such file or directory
compilation terminated.
< builtin >: recipe for target 'main.o' failed
make: *** [main.o] Error 1
Now it says that it does not find “platform.h” despite it being indicated by the INCLUDES variable that contains the location of the header file. Also, it is using the built-in recipe for generating the object files and fails.
So I am stuck at this point, the idea is building the output executable, the map file, the object files and its dependencies files when executing “make build PLATFORM=HOST”.
At the beginning I wrote the build target just for generating the output, the map and object files and did work and then after doing the modifications for generating the dependency files I got lost with this error.
The other recipes for generating preproceessed files, assembly files and doing a clean were working ok.
You can clone the folder with all the needed files from: https://github.com/Fornaso/C1M2.git
Thank you all in advance.
Here is my Makefile:
#******************************************************************************
# Copyright (C) 2017 by Alex Fosdick - University of Colorado
#
# Redistribution, modification or use of this software in source or binary
# forms is permitted as long as the files maintain this copyright. Users are
# permitted to modify this and use it to learn about the field of embedded
# software. Alex Fosdick and the University of Colorado are not liable for any
# misuse of this material.
#
#******************************************************************************
# Modified on April 2020 by Adrián Fornaso
#------------------------------------------------------------------------------
# Simple Makefile for multitarget build system
#
# Use: make [TARGET] [PLATFORM-OVERRIDES]
#
# Build Targets:
#
# build - Builds and links all source files and genereates:
#
# c1m2.map - Map file for the full build
# *.d - Dependency Files for each source file
# *.o - Individual object files
# c1m2.out - Output Executable file
#
#<FILE>.i - Builds <FILE>.i preprocessed file.
#<FILE>.asm - Builds <FILE>.i assembly file.
#<FILE>.o - Builds <FILE>.o object file.
#compile-all - Compile all objects but do NOT link them.
#clean - Removes all generated files.
#
# Platform Overrides: Conditionally assign the appropriate compiler flags,
# linker flags, and architecture flags. The target platform
# must be provided at the command line with the make
# command to set the platform you are compiling for.
#
# PLATFORM = MSP432 - The target embedded system will use
# the cross compiler, arm-none-eabi-gcc.
# PLATFORM = HOST - The host embedded system will use the
# native compiler, gcc.
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
#General Flags (Both Platforms)
#
# -Wall Enable All Warning Messages (CFLAGS)
# -Werror Treats All Warnings as Errors(CFLAGS)
# -g Generate Debugging Info in Executable (CFLAGS)
# -O0 The level of optimization (-O0, -O1, -O2, -O3)) (LDFLAGS)
# -std=c99 The C standard set (CFLAGS)
#
#------------------------------------------------------------------------------
#Target name
BASENAME = c1m2
TARGET = $(BASENAME).out
#General Flags
COMMONCFLAGS = -Wall -Werror -g -std=c99
COMMONLDFLAGS = -Wl,-O0,-Map=$(BASENAME).map
#No spaces after commas after -Wl option.
CPPFLAGS = -E
# -E flag makes the compiler stop in the preprocessed output
#Compile time switches
ifeq ($(PLATFORM), MSP432)
INCLUDES = -I../includes/common \
-I../includes/msp432 \
-I../includes/CMSIS
SOURCES = main.c \
memory.c \
interrupts_msp432p401r_gcc.c \
startup_msp432p401r_gcc.c \
system_msp432p401r.c
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = armv7e-m
SPECS = nosys.specs
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
LDFLAGS = $(COMMONLDFLAGS), -T=$(LINKER_FILE)
CFLAGS = $(COMMONCFLAGS) -D$(PLATFORM) -mcpu=$(CPU) \
-march=$(ARCH) --specs=$(SPECS)
OBJDUMP = arm-none-eabi-objdump
endif
ifeq ($(PLATFORM), HOST)
INCLUDES = -I../includes/common
SOURCES = main.c \
memory.c
CC = gcc
LD = ld
LDFLAGS = $(COMMONLDFLAGS)
CFLAGS = $(COMMONCFLAGS) -D$(PLATFORM)
OBJDUMP = objdump
endif
#Listing object files:
OBJECTS = $(SOURCES:.c=.o)
# 1. --------------------------------------------------------------------------
# Complete build: c1m2.map - Map file for the full build
# *.d - Dependency Files for each source file
# *.o - Individual object files
# c1m2.out - Output Executable file
# LDFLAGS contains the flags for creating the *.map file
.PHONY: build
build: $(TARGET) $(OBJECTS)
$(TARGET):
$(CC) $(CFLAGS) $(LDFLAGS) $(SOURCES) $(INCLUDES) -o $#
# 2. --------------------------------------------------------------------------
# //// Generates the object files of all c-program implementation files and its
# dependecies. ///////////////////////////////////////////////////////////
#This implementation places dependency files into a subdirectory named .deps.
DEPDIR := .deps
DEPFLAGS = -MT $# -MD -MP -MF $(DEPDIR)/$*.d
# Delete the built-in rules for building object files from .c files, so that
# our rule is used instead.
#%.o: %.c
# Our rule for building object files with its dependency
%.o: %.c $(DEPDIR)/%.d | $(DEPDIR)
$(CC) $(DEPFLAGS) -c $(CFLAGS) $(INCLUDES) -o $# $^
# Declare a rule for creating the dependency directory if it doesn’t exist.
$(DEPDIR): ; #mkdir -p $#
# Generate a list of all the dependency files that could exist.
DEPFILES := $(SRCS:%.c=$(DEPDIR)/%.d)
# Mention each dependency file as a target, so that make won’t fail if the file
# doesn’t exist.
$(DEPFILES):
# 2 bis. ----------------------------------------------------------------------
# /// Generates the object file of all c-program implementation files. ////////
#%.o: %.c
# $(CC) -c $(CFLAGS) $(INCLUDES) -o $# $^
# 3. --------------------------------------------------------------------------
# /// Compile all objects but do NOT link them. ///////////////////////////////
.PHONY: compile-all
compile-all: $(SOURCES)
$(CC) -c $(CFLAGS) $(INCLUDES) $^
# 4. --------------------------------------------------------------------------
# /// Generates the preprocessed output of all c-program implementation files.
%.i: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(INCLUDES) -o $# $^
# 5. --------------------------------------------------------------------------
# /// Create assembler file of a C source. ////////////////////////////////////
%.asm: %.c
$(CC) -S $(CFLAGS) $(INCLUDES) $< -o $#
# -S flag tells the compiler just generate the assembly file
# 6. --------------------------------------------------------------------------
# /// Removes all compiled objects, preprocessed outputs, assembly outputs,
# executable files and build output files. ////////////////////////////////
.PHONY: clean
clean:
rm -f $(OBJECTS) $(TARGET) $(BASENAME).map *.asm *.i
rm -r .dep
#End of file
There are two small mistakes which took me quite a while to see:
DEPFILES := $(SRCS:%.c=$(DEPDIR)/%.d) has to be DEPFILES := $(SOURCES:%.c=$(DEPDIR)/%.d) - otherwise DEPFILES is empty since SRCS is undefined.
In $(CC) $(DEPFLAGS) -c $(CFLAGS) $(INCLUDES) -o $# $^ the $^ (all the prerequisites) expands to e. g. main.c .deps/main.d, so a not yet existing .deps/main.d is passed as an input file; we want $*.c instead of $^.
Another minor error is:
rm -r .dep should be rm -r .deps or rm -r $(DEPDIR).
I was making a makefile for cross-compilation between a host and arm based microcontroller. So how do I add a specific library to the recipe of the makefile?
include sources.mk
ifeq ($(PLATFORM),MSP432)
# Platform Overrides
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = thumb
SPECS = nosys.specs
CPP = -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS) -DMSP432
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
endif
ifeq ($(PLATFORM),HOST)
CC = gcc
CPP= DHOST
endif
TARGET =c1m2
LDFLAGS = -Wl,-Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -Wall -Werror -g -O0 -$(CPP) -I/Desktop/ese-coursera-
course1/assessments/m2/include/common/platform.h
-std=c99
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
%.o : %.c
$(CC) -c $< $(CFLAGS) -o $#
OBJS = $(SOURCES:.c=.o)
$(TARGET).out: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
Is this the right way of doing it?(all the tabs and indents for the make file has been given properly, though it is not seen in the code here)
Iam getting this as the error
main.c:23:10: fatal error: platform.h: No such file or directory
#include "platform.h"
^~~~~~~~~~~~
compilation terminated.
Makefile:67: recipe for target 'main.o' failed
make: *** [main.o] Error 1
Also this is my source.mk file
SOURCES = Desktop/ese-coursera-course1/assessments/m2/src
# Add your include paths to this variable
INCLUDES = Desktop/ese-coursera-course1/assessments/m2/include/common/platform.h
Can anyone help me out?
First, try to make sure all paths you give are relative to the Makefile.
I'm surprised your compiler actually does anything since your SOURCES variable is a directory, not a list of .c files. It should probably look like:
SOURCES = src/main.c
this will make OBJS contain src/main.o and the implicit rule will be able to fire.
Next, the INCLUDES variable should reference a directory using the -I flag, like so:
INCLUDES = -Iinclude/common
You should then use it in the CFLAGS definition as follows:
CFLAGS = -Wall -Werror -g -O0 -$(CPP) $(INCLUDES) -std=c99
Other things I noticed:
Your LDFLAGS unconditionally uses the msp432p401r.lds linker script, even in the HOST case. This should probably be added conditionally in the ifeq block like so: LDFLAGS += -T msp432p401r.lds. You should be careful not to overwrite LDFLAGS later with LDFLAGS=, so it is best if you move the definition of CFLAGS and LDFLAGS to the top of the file or always use += to modify these variables.
Following on from that: if your link step uses the linker script, you should add an explicit rule that encodes this dependency: $(TARGET).out: $(LINKER_FILE).
The build -> all -> $(TARGET).out dependency chain is a bit redundant. Why not make build directly depend on $(TARGET).out?
When I compile using my makefile I get these warnings:
clang: warning: -lllist: 'linker' input unused [-Wunused-command-line-argument]
clang: warning: argument unused during compilation: '-L./bin' [-Wunused-command-line-argument]
This is probably because I have messed something up in my Makefile (below). Am I not linking the lib properly? Can anyone point me toward the problem?
all: list parser
parser: list parserCal bin/LinkedListAPI.o bin/CalendarParser.o
ar cr bin/libcparser.a bin/LinkedListAPI.o bin/CalendarParser.o
list: listparser bin/LinkedListAPI.o
ar cr bin/libllist.a bin/LinkedListAPI.o
listparser: src/LinkedListAPI.c include/LinkedListAPI.h
gcc -Wall -std=c11 -c -Iinclude src/LinkedListAPI.c -o bin/LinkedListAPI.o
parserCal: src/CalendarParser.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
gcc -Wall -std=c11 -c -L./bin -lllist -Iinclude src/CalendarParser.c -o bin/CalendarParser.o
TEST: list parser main.c
gcc -Wall -std=c11 -Iinclude main.c -o bin/runMe -L./bin -lllist -lcparser
clean:
rm bin/*.o bin/*.a
The immediate problem is in this rule:
TEST: list parser main.c
gcc -Wall -std=c11 -c -Iinclude main.c -o bin/runMe -L./bin -lllist -lcparser
The option -c means only compile, do not link, so any linker-related command line arguments are ignored, therefore you get that warning. Remove -c and it will work.
That said, this Makefile is "messed up". Normally, your targets should be the files created, e.g.
bin/libllist.a: listparser bin/LinkedListAPI.o
ar cr bin/libllist.a bin/LinkedListAPI.o
The way you do it, make is not more useful than a shell script, as it doesn't know which files are created and can't check whether rebuilding is necessary. Also, it would stop working at all if there was by accident a file named list. If you have rules that don't create a file, you must tell make about it by putting them as phony targets, e.g.:
.PHONY: all clean
a makefile is set of sequential things that need to be done, however, if a certain created file has no changes in its' dependency files, then that file will not be recreated.
It is best to be very specific about what specific utility program is to be run.
targets in the make file that don't actually create a file with the same name should be flagged using the .PSEUDO operator.
here is an example of a correctly written makefile, using the posted makefile as the basis: I've included a few comments in the makefile to clarify what is being done at each step
notice there (in this make file) is no mixing of compile parameters and rules with link parameters and rules
# use ':=' so the macro will only be evaluated once
# using just '=' results in the macro being reevaluated each time it is referenced.
# notice that desirable parameters are being set inside the macro definitions
CFLAGS := -Wall -Wextra -pedantic -std=c11
RM := /bin/rm -f
CC := /bin/gcc
AR := /bin/ar cr
# tell 'make' that these targets do not produce a file of the same name
.PSEUDO: all clean
# this is the first target in this makefile
# it lists the three 'final' targets
# so each of those target rules will be executed
all: bin/runMe bin/libcparser.a bin/libllist.a
# link step
bin/runMe: main.o bin/CalendarParser.o bin/LinkedListAPI.o
$(CC) main.o bin/CalendarParser.o bin/LinkedListAPI.o -o bin/runMe -L./bin -lllist -lcparser
# archive creation step
bin/libcparser.a: bin/LinkedListAPI.o bin/CalendarParser.o
$(AR) bin/libcparser.a bin/LinkedListAPI.o bin/CalendarParser.o
# archive creation step
bin/libllist.a: bin/LinkedListAPI.o
$(AR) bin/libllist.a bin/LinkedListAPI.o
# notice the archive targets and final runnable file
# reference certain dependencies.
# when a dependency is not available or not 'up to date'
# then the associated rule is executed to bring that dependency 'up to date'
# compile ./src/LinkedListAPI.c to create ./bin/LinkedListAPI.o
bin/LinkedListAPI.o: src/LinkedListAPI.c include/LinkedListAPI.h
$(CC) $(CFLAGS) -c src/LinkedListAPI.c -o bin/LinkedListAPI.o -Iinclude
# compile ./src/CalendarParser.c to create ./bin/calendarParser.o
bin/CalendarParser.o: src/CalendarParser.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
$(CC) $(CFLAGS) -c src/CalendarParser.c -o ./bin/CalendarParser.o -Iinclude
# compile main.c to create main.o
main : main.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
$(CC) $(CFLAGS) -c main.c -o main.o -Iinclude
clean:
$(RM) bin/*.o bin/*.a
This is an incredibly simple question, but I'm new to makefiles. I am trying to make a makefile that will compile two independent programs:
program1:
gcc -o prog1 program1.c
program2:
gcc -o prog2 program2.c
All the examples online go into way more details than I need and are confusing! All I really want it to do is to run the two gcc lines. What am I doing wrong?
Do it like so
all: program1 program2
program1: program1.c
gcc -o program1 program1.c
program2: program2.c
gcc -o program2 program2.c
You said you don't want advanced stuff, but you could also shorten it like this based on some default rules.
all: program1 program2
program1: program1.c
program2: program2.c
Pattern rules let you compile multiple c files which require the same compilation commands using make as follows:
objects = program1 program2
all: $(objects)
$(objects): %: %.c
$(CC) $(CFLAGS) -o $# $<
############################################################################
# 'A Generic Makefile for Building Multiple main() Targets in $PWD'
# Author: Robert A. Nader (2012)
# Email: naderra at some g
# Web: xiberix
############################################################################
# The purpose of this makefile is to compile to executable all C source
# files in CWD, where each .c file has a main() function, and each object
# links with a common LDFLAG.
#
# This makefile should suffice for simple projects that require building
# similar executable targets. For example, if your CWD build requires
# exclusively this pattern:
#
# cc -c $(CFLAGS) main_01.c
# cc main_01.o $(LDFLAGS) -o main_01
#
# cc -c $(CFLAGS) main_2..c
# cc main_02.o $(LDFLAGS) -o main_02
#
# etc, ... a common case when compiling the programs of some chapter,
# then you may be interested in using this makefile.
#
# What YOU do:
#
# Set PRG_SUFFIX_FLAG below to either 0 or 1 to enable or disable
# the generation of a .exe suffix on executables
#
# Set CFLAGS and LDFLAGS according to your needs.
#
# What this makefile does automagically:
#
# Sets SRC to a list of *.c files in PWD using wildcard.
# Sets PRGS BINS and OBJS using pattern substitution.
# Compiles each individual .c to .o object file.
# Links each individual .o to its corresponding executable.
#
###########################################################################
#
PRG_SUFFIX_FLAG := 0
#
LDFLAGS :=
CFLAGS_INC :=
CFLAGS := -g -Wall $(CFLAGS_INC)
#
## ==================- NOTHING TO CHANGE BELOW THIS LINE ===================
##
SRCS := $(wildcard *.c)
PRGS := $(patsubst %.c,%,$(SRCS))
PRG_SUFFIX=.exe
BINS := $(patsubst %,%$(PRG_SUFFIX),$(PRGS))
## OBJS are automagically compiled by make.
OBJS := $(patsubst %,%.o,$(PRGS))
##
all : $(BINS)
##
## For clarity sake we make use of:
.SECONDEXPANSION:
OBJ = $(patsubst %$(PRG_SUFFIX),%.o,$#)
ifeq ($(PRG_SUFFIX_FLAG),0)
BIN = $(patsubst %$(PRG_SUFFIX),%,$#)
else
BIN = $#
endif
## Compile the executables
%$(PRG_SUFFIX) : $(OBJS)
$(CC) $(OBJ) $(LDFLAGS) -o $(BIN)
##
## $(OBJS) should be automagically removed right after linking.
##
veryclean:
ifeq ($(PRG_SUFFIX_FLAG),0)
$(RM) $(PRGS)
else
$(RM) $(BINS)
endif
##
rebuild: veryclean all
##
## eof Generic_Multi_Main_PWD.makefile
all: program1 program2
program1:
gcc -Wall -o prog1 program1.c
program2:
gcc -Wall -o prog2 program2.c
all: program1 program2
program1:
gcc -Wall -ansi -pedantic -o prog1 program1.c
program2:
gcc -Wall -ansi -pedantic -o prog2 program2.c
I rather the ansi and pedantic, a better control for your program. It wont let you compile while you still have warnings !!
A simple program's compilation workflow is simple, I can draw it as a small graph: source -> [compilation] -> object [linking] -> executable. There are files (source, object, executable) in this graph, and rules (make's terminology). That graph is definied in the Makefile.
When you launch make, it reads Makefile, and checks for changed files. If there's any, it triggers the rule, which depends on it. The rule may produce/update further files, which may trigger other rules and so on. If you create a good makefile, only the necessary rules (compiler/link commands) will run, which stands "to next" from the modified file in the dependency path.
Pick an example Makefile, read the manual for syntax (anyway, it's clear for first sight, w/o manual), and draw the graph. You have to understand compiler options in order to find out the names of the result files.
The make graph should be as complex just as you want. You can even do infinite loops (don't do)! You can tell make, which rule is your target, so only the left-standing files will be used as triggers.
Again: draw the graph!.
SRC = a.cpp b.cpp
BIN = $(patsubst %.cpp,%,$(SRC))
all: $(BIN)
clean:
rm -f $(BIN)
.PHONY: all clean
make all will do:
c++ a.cpp -o a
c++ b.cpp -o b
If you set CXX and CXXFLAGS variables make will use them.
This will compile all *.c files upon make to executables without the .c extension as in gcc program.c -o program.
make will automatically add any flags you add to CFLAGS like CFLAGS = -g Wall.
If you don't need any flags CFLAGS can be left blank (as below) or omitted completely.
SOURCES = $(wildcard *.c)
EXECS = $(SOURCES:%.c=%)
CFLAGS =
all: $(EXECS)