How to add a library path to a makefile? - c

I was making a makefile for cross-compilation between a host and arm based microcontroller. So how do I add a specific library to the recipe of the makefile?
include sources.mk
ifeq ($(PLATFORM),MSP432)
# Platform Overrides
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = thumb
SPECS = nosys.specs
CPP = -mcpu=$(CPU) -m$(ARCH) --specs=$(SPECS) -DMSP432
# Compiler Flags and Defines
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld
endif
ifeq ($(PLATFORM),HOST)
CC = gcc
CPP= DHOST
endif
TARGET =c1m2
LDFLAGS = -Wl,-Map=$(TARGET).map -T $(LINKER_FILE)
CFLAGS = -Wall -Werror -g -O0 -$(CPP) -I/Desktop/ese-coursera-
course1/assessments/m2/include/common/platform.h
-std=c99
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
%.o : %.c
$(CC) -c $< $(CFLAGS) -o $#
OBJS = $(SOURCES:.c=.o)
$(TARGET).out: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) $(LDFLAGS) -o $#
Is this the right way of doing it?(all the tabs and indents for the make file has been given properly, though it is not seen in the code here)
Iam getting this as the error
main.c:23:10: fatal error: platform.h: No such file or directory
#include "platform.h"
^~~~~~~~~~~~
compilation terminated.
Makefile:67: recipe for target 'main.o' failed
make: *** [main.o] Error 1
Also this is my source.mk file
SOURCES = Desktop/ese-coursera-course1/assessments/m2/src
# Add your include paths to this variable
INCLUDES = Desktop/ese-coursera-course1/assessments/m2/include/common/platform.h
Can anyone help me out?

First, try to make sure all paths you give are relative to the Makefile.
I'm surprised your compiler actually does anything since your SOURCES variable is a directory, not a list of .c files. It should probably look like:
SOURCES = src/main.c
this will make OBJS contain src/main.o and the implicit rule will be able to fire.
Next, the INCLUDES variable should reference a directory using the -I flag, like so:
INCLUDES = -Iinclude/common
You should then use it in the CFLAGS definition as follows:
CFLAGS = -Wall -Werror -g -O0 -$(CPP) $(INCLUDES) -std=c99
Other things I noticed:
Your LDFLAGS unconditionally uses the msp432p401r.lds linker script, even in the HOST case. This should probably be added conditionally in the ifeq block like so: LDFLAGS += -T msp432p401r.lds. You should be careful not to overwrite LDFLAGS later with LDFLAGS=, so it is best if you move the definition of CFLAGS and LDFLAGS to the top of the file or always use += to modify these variables.
Following on from that: if your link step uses the linker script, you should add an explicit rule that encodes this dependency: $(TARGET).out: $(LINKER_FILE).
The build -> all -> $(TARGET).out dependency chain is a bit redundant. Why not make build directly depend on $(TARGET).out?

Related

undefined reference to 'pow' using makefile

I'm trying to use the pow function but the make command gives me this error. I did #include<math.h> at the start of the file.
Compiling the .c file on its own using gcc test.c -o test -lm works fine, but as part of my assignment, I have to use the makefile my instructors gave me. (What I'm guessing to be) its most relevant portion looks like this:
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
What should I try, and can I fix this without changing the contents of the makefile? Thank you.
Edit:
Including all of my code would be a mess, but this is what causes the error:
int max = pow(2, n);
(n is an int)
full makefile:
###############################################
# Makefile for compiling the program skeleton
# 'make' build executable file 'PROJ'
# 'make doxy' build project manual in doxygen
# 'make all' build project + manual
# 'make clean' removes all .o, executable and doxy log
###############################################
PROJ = proj # the name of the project
CC = gcc # name of compiler
DOXYGEN = doxygen # name of doxygen binary
# define any compile-time flags
CFLAGS = -std=c99 -Wall -O -Wuninitialized -Wunreachable-code -pedantic
LFLAGS = -lm
###############################################
# You don't need to edit anything below this line
###############################################
# list of object files
# The following includes all of them!
C_FILES := $(wildcard *.c)
OBJS := $(patsubst %.c, %.o, $(C_FILES))
# To create the executable file we need the individual
# object files
$(PROJ): $(OBJS)
$(CC) $(LFLAGS) -g -o $(PROJ) $(OBJS)
# To create each individual object file we need to
# compile these files using the following general
# purpose macro
.c.o:
$(CC) $(CFLAGS) -g -c $<
# there is a TAB for each identation.
# To make all (program + manual) "make all"
all :
make
make doxy
# To make all (program + manual) "make doxy"
doxy:
$(DOXYGEN) *.conf &> doxygen.log
# To clean .o files: "make clean"
clean:
rm -rf *.o doxygen.log html

Fatal error when trying to set up fftw3 with c, MacOS Monterey

When trying to compile my c code I keep getting basic.c:5:10: fatal error: 'fftw3.h' file not found. I am compiling my c code using MacOS terminal and have Xcode installed.
I'm trying to write some c code which uses the fftw-3 library. fftw-3 has been installed using sudo port install fftw-3 and I have entered port contents fftw-3 which returned:
/opt/local/include/dfftw.h
/opt/local/include/dfftw_threads.h
/opt/local/include/drfftw.h
/opt/local/include/drfftw_threads.h
/opt/local/include/fftw_f77.i
/opt/local/lib/libdfftw.2.dylib
/opt/local/lib/libdfftw.a
/opt/local/lib/libdfftw.dylib
/opt/local/lib/libdfftw_threads.2.dylib
/opt/local/lib/libdfftw_threads.a
/opt/local/lib/libdfftw_threads.dylib
/opt/local/lib/libdrfftw.2.dylib
/opt/local/lib/libdrfftw.a
/opt/local/lib/libdrfftw.dylib
/opt/local/lib/libdrfftw_threads.2.dylib
/opt/local/lib/libdrfftw_threads.a
/opt/local/lib/libdrfftw_threads.dylib
/opt/local/share/info/fftw.info
/opt/local/share/info/fftw.info-1
/opt/local/share/info/fftw.info-2
/opt/local/share/info/fftw.info-3
/opt/local/share/info/fftw.info-4
/opt/local/share/info/fftw.info-5
I have been using a makefile and am trying to work out what needs including in it. At the moment I have:
# define the name of your source file(s)
SRCS = basic.c
# define the name of the object files(s) - we can do this automatically
OBJS = $(SRCS:.c=.o)
# tell MAKE which compiler to use
CCOMP = gcc
# flags for the compiler
# don't forget the -O3
CFLAGS = -Wall -O3 -fstrict-aliasing -Iinclude
#CFLAGS = -c -Wall -Iinclude
# flags for the linker. note -lm for the math library
LDFLAGS = -O3 -lm -L/opt/lib -I/opt/lib -L/opt/local/include -I/opt/lib
# the name of your executable file (the target) - here we put it in the top directory
TARGET = basic
# actions
all: $(OBJS)
$(CCOMP) -o $(TARGET) $(OBJS) $(LDFLAGS)
%.o: %.c
$(CCOMP) -c -o $# $< $(CFLAGS)
# delete all objects and target
clean:
rm -f $(OBJS) $(TARGET)
I'm not sure if the #CFLAGS and #LDFLAGS sections are correct? I would appreciate troubleshooting and any advice on what I need to do to get this working. Thanks!

Makefile Stops Building Files After First .o In Out-of-Source Build

I have a bit of a huge Makefile that basically works as I want it to.
Issue: The problem I'm having is that the makefile only checks if the first .o needs updating and not if any others do. I'm not sure what part of my makefile is in error.
Context: I have project structure like this:
quendor
src
main.c
options.c
quendor.h
Makefile
When my Makefile builds, it constructs a build directory and things look as follows:
quendor
build
src
main.d
main.o
options.d
options.o
src
main.c
options.c
quendor.h
Makefile
To See the Problem: Now let's say I don't change my main.c but I do change my options.c file. In that case, when I run make again I get this:
make: 'build/./src/main.o' is up to date.
I'm not sure if this is because it's building into a build/src directory rather than just build as I intended.
Here is the full Makefile and I'm including all of it just because I'm not sure what might be a problem and I don't want to make unwarranted assumptions.
.PHONY : all clean
NAME := quendor
PLATFORM := windows
CC := gcc
LINK := gcc
BUILD_DIR ?= ./build
SRC_DIR ?= ./src
ifeq ($(PLATFORM), windows)
TARGET ?= quendor.exe
else
TARGET ?= quendor
endif
ifeq ($(CC), gcc)
CFLAGS += -std=c11 -Wall -Wextra -Wpedantic -Wconversion -Wmissing-prototypes -Wshadow -MMD -MP
LDFLAGS +=
OPT +=
endif
SRCS := $(wildcard $(SRC_DIR)/*.c)
OBJS := $(SRCS:%.c=$(BUILD_DIR)/%.o)
DEPS := $(OBJS:%.o=%.d)
MKDIR_P ?= #mkdir -p $(dir $#)
-include $(DEPS)
all : $(TARGET)
#echo "Building $(TARGET)"
$(TARGET) : $(OBJS)
$(LINK) $(OPT) -o $# $^ $(LDFLAGS)
$(BUILD_DIR)/%.o : %.c
$(MKDIR_P)
$(CC) $(CFLAGS) -c $< -o $#
clean:
$(RM) $(TARGET) -r $(BUILD_DIR)
This may be an artifact of how StackOverflow is parsing my Makfile but I do notice that it's showing different syntax highlighting after this line:
SRCS := $(wildcard $(SRC_DIR)/*.c)
The problem is that you are including the dependencies before you define the all rule:
-include $(DEPS)
all : $(TARGET)
If you don't specify a particular target to build on the command line (e.g., if you don't run make all) then make chooses the first explicit target in the makefile (and any included makefiles!!) as the target to build.
I assume that the dependency definitions in the $(DEPS) variable define main.o as a target and since that comes before all, it's the only thing that's run by default.
Move the -include statement later in the makefile (I typically put these all at the end of the makefile) and it will work.

Makefile for a single target with multiple .c and .h dependencies

I have this hello-world.c that I'd like to compile to hello-world binary. But hello-world.c depends on a few functions defined in ../helpers/a.c and ../helpers/b.c, and each of those helpers include ../helpers/a.h and ../helpers/b.h respectively.
My current Makefile looks like
CC = #gcc
CFLAGS = -g -Wall -Wextra -Werror
CFLAGS +=
LDLIBS =
LDLIBS +=
OBJS = ../helpers/a.o ../helpers/b.o
SOURCES = hello-world.c
DESTS = hello-world
new: clean all
clean:
#rm -rf *.o */*.o $(DESTS)
all: $(OBJS) $(DESTS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%: %.c
$(CC) $(CFLAGS) -o $# $<
but it doesn't work, returning make: *** No rule to make target `../helpers/a.o', needed by `all'. Stop.
I understand that Makefile doesn't seem to see the rule for %.o, but I don't see why.
Edit: Makefile debug:
alexandernst#stupidbox:/media/sf_procmon/procmon$ make --debug=b
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
This program built for x86_64-pc-linux-gnu
Reading makefiles...
Updating goal targets....
File `new' does not exist.
File `clean' does not exist.
Must remake target `clean'.
Successfully remade target file `clean'.
File `all' does not exist.
File `../helpers/a.o' does not exist.
Must remake target `../helpers/a.o'.
make: *** No rule to make target `../helpers/a.o', needed by `all'. Stop.
This is much easier to get working if you put the Makefile in the parent directory. Then you can write something like this:
CC = gcc
CFLAGS = -g -Wall -Wextra -Werror
CPPFLAGS = -Ihelpers
DESTS = hello-world/hello-world
OBJS = helpers/a.o helpers/b.o hello-world/hello-world.o
# Do not make 'all' depend directly on object files.
all: $(DESTS)
# Clean rules should always be prefixed with '-' to avoid
# errors when files do not exist. Do not use 'rm -r' when
# there shouldn't be directories to delete; do not delete
# wildcards when you can use explicit lists instead.
# Never use '#'.
clean:
-rm -f $(OBJS) $(DESTS)
# An explicit linkage rule is needed for each entry in DESTS.
hello-world/hello-world: hello-world/hello-world.o \
helpers/a.o helpers/b.o
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LIBS)
# The main function of these dependency lists is to prevent
# Make from deleting object files after each build. We also
# take the opportunity to specify header dependencies.
# We rely on the built-in %.o:%.c rule for commands.
hello-world/hello-world.o: hello-world/hello-world.c \
helpers/a.h helpers/b.h
helpers/a.o: helpers/a.c helpers/a.h
helpers/b.o: helpers/b.c helpers/b.h
# This tells Make that 'all' and 'clean' are not files to be created.
.PHONY: all clean
For further exposition of this technique, see the watershed paper 'Recursive Make Considered Harmful' and the associated implementation notes.
I managed to fix my Makefile:
CC = gcc
CFLAGS = -g -Wall -Wextra -Werror
CFLAGS +=
LDLIBS =
LDLIBS +=
OBJS = ../helpers/a.o ../helpers/b.o hello-world.o
SOURCES = hello-world.c
DESTS = hello-world
new: clean all
clean:
#rm -rf *.o */*.o ../helpers/*.o $(DESTS)
all: $(DESTS)
hello-world: $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LIBS)
One of the problems was that a bad clean rule that I wrote had wiped a.c and b.c and Makefile was acting because of this.

make: force recompilation of same objects with different compiler

I want my makefile to build the same binary 2 times, first compiling with gcc and then with mingw. So, I've written this, but it does not work:
OBJ_DIR = obj
SRC_DIR = src
BIN_DIR = bin
INCLUDE = -I./$(SRC_DIR)
LIBS =
_SRCS = print_current_dir.c test_main.c
_OBJS = print_current_dir.o test_main.o
SRCS = $(addprefix $(SRC_DIR)/,$(_SRCS))
OBJS = $(addprefix $(OBJ_DIR)/,$(_OBJS))
all: $(BIN_DIR)/pps-linux $(BIN_DIR)/pps-win32
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) -c -o $# $< $(CFLAGS)
$(BIN_DIR)/pps-linux: CC = cc
$(BIN_DIR)/pps-linux: CFLAGS = -g -Wall $(INCLUDE) $(LIBS)
$(BIN_DIR)/pps-linux: $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $#
$(BIN_DIR)/pps-win32: CC = i586-mingw32msvc-cc
$(BIN_DIR)/pps-win32: CFLAGS = -g -Wall $(INCLUDE) $(LIBS)
$(BIN_DIR)/pps-win32: $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $#
Once it compiles the objects file in $(OBJS) with gcc for the target pps-linux, it tries to build pps-win32 with the very same objects file, obviously failing, and despite the fact that I redefined CC and CFLAGS for the target pps-win32.
Here is the output:
$ make
cc -c -o obj/print_current_dir.o src/print_current_dir.c -g -Wall -I./src
cc -c -o obj/test_main.o src/test_main.c -g -Wall -I./src
cc -g -Wall -I./src obj/print_current_dir.o obj/test_main.o -o bin/pps-linux
i586-mingw32msvc-cc -g -Wall -I./src obj/print_current_dir.o obj/test_main.o -o bin/pps-win32
obj/print_current_dir.o: In function `print_dir':
/home/matteo/Desktop/pps/src/print_dir.c:23: undefined reference to `get_current_dir_name'
/home/matteo/Desktop/pps/src/print_dir.c:25: undefined reference to `puts'
/home/matteo/Desktop/pps/src/print_dir.c:27: undefined reference to `free'
/usr/lib/gcc/i586-mingw32msvc/4.4.4/../../../../i586-mingw32msvc/lib/libmingw32.a(main.o):(.text+0x85): undefined reference to `_WinMain#16'
collect2: ld returned 1 exit status
make: *** [bin/pps-win32] Error 1
How do I force the recompilation of the objects file just compiled with a different compiler?
Thank you.
By making the object files compiler-dependent too, rather than trying to overwrite the same .o file in place with different contents, eg.
LINUX_OBJS = $(addprefix $(LINUX_OBJ_DIR)/,$(_OBJS))
...
$(BIN_DIR)/pps-linux: $(LINUX_OBJS)
NB. you may be able to do it more tidily by just using a target-dependent definition of OBJ_DIR, ie,
$(BIN_DIR)/pps-linux: OBJ_DIR = linux-obj
but I'd have to try it to be sure.
I would suggest using separate OBJ_DIR and BIN_DIR directories to accomplish this, with the names being constructed in part from the compiler vendor:
OBJ_DIR = obj-$(CC)
BIN_DIR = bin-$(CC)
I use a similar approach that has completely separate build directories, and installation directories, with the names constructed from:
compiler vendor
compiler version
architecture
libc version (if linux)
which results in directories named (for example):
gcc_3.4.6-x86-libc_2.3.4
forte_5.10-x64
gcc_4.2.3-x86

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