what i'm doing wrong?
And can you send some helpful links to make my work with makefiles easier and better?
get_next_line.o: file not recognized: File format not recognized
collect2: error: ld returned 1 exit status
Makefile:27: recipe for target 'gnl' failed
make: *** [gnl] Error 1
+++
SRC = gnl.c
OBJ = $(SRC:.c=.o)
INCLUDES = gnl.h
NAME = gnl
CFLAGS = -Wall -Werror -Wextra
CC = gcc
DIR = LIBFT
%.o: %.c $(SRC) $(INCLUDES)
$(CC) $(CFLAGS) -c $<
all: $(NAME)
$(NAME): $(OBJ)
make -C $(DIR)
$(CC) $(CFLAGS) -o $(NAME) $(OBJ) -L. $(DIR)/libft.a
clean:
make clean -C $(DIR)
rm -f $(OBJ)
fclean:
make fclean -C $(DIR)
rm -f $(NAME)
re: fclean all
This is not a make error by itself. It says
get_next_line.o: file not recognized: File format not recognized
so that is your problem. Somehow you managed to have a .o file in your directory that is corrupted. Remove it and things will go better.
You have misunderstood the error message. The error message is referring to the file get_next_line.o, not the makefile.
It is the linker (ld) that is reporting the error not make. The command that has failed is that for the target gnl.
It can even be simpler...
It just happened to me with a Makefile.
In the line (in the Makefile) that creates the executable, where there are different names of objects .o, there was a typo. I left the name of the file .cu (CUDA format) instead of .o.
I ran into this error recently, and I have a couple of suggestions that might help. My problem was not a bad .o file, but rather a 32-bit installation rather than a 64-bit installation. If this is the case for you, too, you might get more complete functionality by trying this solution.
In my case, the makefile(s) in question needed different CFLAGS depending on whether the installation was 64-bit or 32-bit. Here are some lines from the README of the project I was trying to make.
By default, the C/C++ software are compiled in 32 bits with the options (-Os) but can be compiled in 64 bits, -m64 is added to the CFLAGS variable in <certain makefiles in the project are listed>
My suggestion is to first try adding -m64 to your CFLAGS. If that doesn't work, delete the -m64 and replace it with -Os.
That is, first try having the following line:
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -m64
Then, from the command line, run
make clean
Followed by whatever make commands you use for your install.
If that doesn't work, change the line in question to
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -Os
Then make clean and the other make stuff.
If some of the C objects are 64-bit and some are 32-bit (I don't know if such a situation actually exists), you might have to do something different.
This worked in my case, details of which you can see here.
Please comment to let me know if it works for you.
Related
I've written multiple C programs in different files and I want to run all three of them in the same time, on the same argv:
That's what I tried so far but its only running the last program digcmp.c:
CC=gcc
a_OBJS=lexcmp.o
b_OBJS=lencmp.o
c_OBJS=digcmp.o
EXEC=lex len dig
DEBUG = -g
CFLAGS = -std=c99 -Wall -Werror $(DEBUG) #if you have CFLAGS you do not have to write for each file $(CC) -c $*.c!!!
lex: $(b_OBJS)
$(CC) $(a_OBJS) -o $#
len: $(b_OBJS)
$(CC) $(b_OBJS) -o $#
dig: $(c_OBJS)
$(CC) $(c_OBJS) -o $#
lexcmp.o: lexcmp.c
lencmp.o: lencmp.c
digcmp.o: digcmp.c
clean:
rm -f lex $(a_OBJS)
rm -f len $(b_OBJS)
rm -f dig $(c_OBJS)
The make program have many implicit rules. In fact they are what makes your lexcmp.o: lexcmp.c (etc.) rules work.
All you need is to list the rules to make the executable programs themselves:
lexcmp: lexcmp.o
lencmp: lencmp.o
digcmp: digcmp.o
The above is a perfectly fine Makefile on its own, and if you run e.g.
$ make lencmp
then the lencmp.c source file will be built into the object file lencmp.o which will then be linked into the executable lencmp program.
If you want specific compilation flags when building just set the CFLAGS variable and it will be used automatically. I also recommend a default target which might list all executable targets as dependencies to build all of them:
CFLAGS = -Wall -Wextra
.PHONY: all
all: lexcmp lencmp digcmp
This should really be enough to build all your executable files (skipping the object-file intermediate stage) with the flags you want.
The .PHONY target tells make that it's not supposed to generate a file with the name all.
My working directory looks like this:
main.c
Makefile
my_memmove.h
my_memmove.c
c-timer-lib
timer.c
timer.h
My makefile looks like this:
CC := gcc
CFLAGS := -std=gnu99 -g -Wall -Wextra -Ic-timer-lib
TARGET := output
output: main.o my_memmove.o timer.o
$(CC) $(CFLAGS) main.o my_memmove.o timer.o -o $(TARGET)
main.o: main.c
gcc -c main.c
my_memmove.o: my_memmove.c my_memmove.h
gcc -c my_memmove.c
timer.o: c-timer-lib/timer.c c-timer-lib/timer.h
gcc -c c-timer-lib/timer.c -o $#
clean:
rm *.o $(TARGET)
I don't understand why I keep getting the "Makefile: No rule to make target 'timer.c', needed by 'timer.o'. Stop." error. I believe that it's because the timer.c and timer.h files can't be found.
So much confusion here! :)
First, this is definitely wrong:
$(CC) $(CFLAGS) -I main.o ...
The -I main.o tells the compiler that it should use main.o as the name of a directory to search for include files. That clearly won't work. You should remove the -I here.
On to your problem: you have to realize that there are two completely different programs at play here: make which figures out how to run commands, and the commands that are being run, in this case the compiler gcc.
The -I option is an option to the compiler so that the compiler knows where to look for header files that are included by your source code with #include.
That option means nothing to make; it doesn't understand that option. It's just some text to pass to the compiler. Make is looking for the source file timer.c and it can't find it because you haven't told make where it is.
You have to write your rule to look in the correct place, like this:
timer.o: c-timer-lib/timer.c c-timer-lib/timer.h
gcc -c c-timer-lib/timer.c -o $#
(you should always use -o $# so that your compile line puts the output file where make expects to find it, which will be put into the $# variable by make before it evaluates your recipe.)
ETA
Also, are you sure that -DUNITS="ms" is right? We can't tell without seeing how UNITS is used in the source, but I suspect you probably need an extra level of quotes here, like -DUNITS='"ms"'
Really, you are trying to do too much in this makefile. Make already knows how to correctly build object files from source files. If you don't force the issue by writing your own rules, then make's built-in rules will do the job for you. Your makefile can be written like this:
CC := gcc
CFLAGS := -std=gnu99 -g -Wall -Wextra -Ic-timer-lib -DUNITS='"ms"'
TARGET := output
$(TARGET): main.o my_memmove.o c-timer-lib/timer.o
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LDLIBS)
my_memmove.o: my_memmove.h
c-timer-lib/timer.o: c-timer-lib/timer.h
clean:
rm *.o $(TARGET)
make doesn't know which headers your source requires so you have to add the prerequisites by hand, although you can add extra rules to allow it to figure that out for itself.
I downloaded the C source code for single-threaded Linux versions of cubist software. what the code does is it takes the input data and generates the regression tree model.
when compiling the source code using Ubuntu terminal it generated the Executable file with out error.
Here is the makefile
CC = gcc -ffloat-store
OFLAGS = -O3
CFLAGS = -DVerbOpt -g -Wall -O0
LFLAGS = $(S)
SHELL = /bin/csh
src =\
global.c\
xval.c\
cubist.c\
sort.c\
construct.c\
predict.c\
stats.c\
discr.c\
rules.c\
contin.c\
formrules.c\
formtree.c\
getdata.c\
getnames.c\
implicitatt.c\
instance.c\
modelfiles.c\
prunetree.c\
regress.c\
trees.c\
update.c\
utility.c
obj =\
global.o cubist.o construct.o\
formtree.o prunetree.o stats.o discr.o contin.o\
trees.o\
formrules.o rules.o\
instance.o\
predict.o\
regress.o\
xval.o\
getnames.o getdata.o implicitatt.o sort.o\
modelfiles.o\
update.o utility.o\
all:
make cubist
$(CC) $(LFLAGS) $(OFLAGS) -o summary summary.c -lm
# debug version (including verbosity option)
cubistdbg:\
$(obj) defns.i extern.i text.i Makefile
$(CC) $(CFLAGS) -o cubistdbg $(obj) -lm
# production version
cubist:\
$(src) defns.i text.i Makefile
cat defns.i $(src)\
| egrep -v 'defns.i|extern.i' >cubistgt.c
$(CC) $(LFLAGS) $(OFLAGS) -o cubist cubistgt.c -lm
strip cubist
rm cubistgt.c
$(obj): Makefile defns.i extern.i text.i
.c.o:
$(CC) $(CFLAGS) -c $<
When i try to do similar work in windows i got error message
$ make all
make cubist
make: /bin/csh: Command not found
make: *** [Makefile:56: all] Error 127
But when i try by removing SHELL = /bin/csh from Makefile it worked. My question here is does it has negative effect on the software or
how could i fix it with out removing SHELL = /bin/csh.
thank you very much
My guess is that by removing the line SHELL = /bin/csh your result is ok.
/bin/csh is a shell (command line interface, command processor, command prompt) used mostly in unix. In your makefile it is defined, but not referenced (not used).
Sometimes makefiles can need a shell (command processor) in order to execute some task, but it is up to the makefile - I mean, the person writing the makefile chooses to use that functionality or not and, if used, can (or must) specify which shell to use. This is not your case, now.
I am in the process of porting some code that was developed in the codeblocks IDE. I am transferring it to a Linux server where I can only use the command line to compile the code. The code is quite large (maybe 100 files) and I need to update the include commands in many files. For when I try to compile it errors on for instance: #include <gsl/gsl_math.h> with a file cannot be found error. I am assuming it cannot be found because the location of the gsl folder was declared in one of the search directory field options in the IDE. I could go through each file an update to the correct path, but is there a better way of doing this for use with a makefile?
Thanks!
EDIT Makefile In Question
# -c : do not link, just create object file
# -o : output file name
CFLAGS += -c -O2 -I../ctraj -I../cspice/include -I../SGP4 -I../cconj -I../GSL-1.13/include
LIBS = -L../ctraj -lctraj -L../cspice/lib -lcspice -L../SGP4 -lsgp4 -L../cconj -lcconj -L./ -lgsl-0 -lgslcblas-0 -lm
DEPS = light.h ../ctraj/ctraj.h ../cconj/cconj.h
OBJ = light.o tle.o propagator.o orbitfit.o conjunction.o light_displacement.o forces_LF.o
OUT = light.exe
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
light: $(OBJ)
cd ../ctraj/; make
gcc -o $(OUT) $(OBJ) $(LIBS)
clean:
rm *.o $(OUT)
Edit 2
Folder Structure
light->(GSL-1.13, Light, cconj, ctraj)
the makefile is inside the Light folder.
Error Message
cd ../ctraj/; make
make[1]: Entering directory `/light/ctraj'
gcc -o forces.o forces.c -c -Wall -Wno-maybe-uninitialized -Wno-unused-but-set-variable -O2 -I../cspice/include -Inrlmsise
In file included from ../Light/../cconj/cconj.h:12:0,
from ../Light/light.h:13,
from forces.c:3:
../Light/../cconj/../GSL-1.13/include/gsl/gsl_blas.h:26:28: fatal error: gsl/gsl_vector.h: No such file or directory
compilation terminated.
make[1]: *** [forces.o] Error 1
make[1]: Leaving directory /light/ctraj'
make: *** [light] Error 2
EDIT 3
Second makefile in cconj
# -c : do not link, just create object file
# -o : output file name
#-L../cconj -lcconj
CFLAGS += -c -O2 -I./ -I../GSL-1.13/include
LIBS = -L./ -lgsl-0 -lgslcblas-0 -lm
INC= -I../GSL-1.13/include
DEPS = cconj.h
OBJ = cconj_util.o ellipse_intersect.o collision_prob_real.o rcs2size.o
OUT = libcconj.a
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
cconj: $(OBJ)
ar rcs $(OUT) $(OBJ)
clean:
rm *.o $(OUT)
Try adding this line to your makefile, and tell us if it works:
CFLAGS += -I../GSL-1.13/include
In order to compile source code and produce object files, Make must use a rule. (If you don't put such a rule in the makefile, Make has a default rule for that purpose.) It looks something like this:
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
Without digging too deeply into how that works, we can say that CFLAGS is a list of arguments to be passed to the compiler. When we add -I../GSL-1.13/include, we tell the compiler "if you want to #include something and can't find it elsewhere, look in ../GSL-1.13/include".
If this approach doesn't work, then there's probably a rule in the makefile we must find and alter.
EDIT:
The problem isn't in this makefile (which already contains a reference to GSL-1.13/include). In this command:
cd ../ctraj/; make
this makefile launches a second Make process, which uses the Makefile in light/cconj/. According to the compiler output (gcc -o forces.o ...), that makefile does not include the reference. So try adding the same line there, and if that doesn't work, post that makefile and we'll keep looking.
Use -I option of gcc to specify where to look for includes.
I am modifying an old makefile in order to build a C extension for postgreSQL. The Makefile currently looks like this:
PGLIB = /usr/lib/postgresql/8.4/lib
PQINC = /usr/include/postgresql/8.4/server
CC=gcc
override CFLAGS+= $(CFLAGS_SL) -DPG_AGGREGATE
SHLIB = pg_myextlib
SRC = foo.c \
foobar.c
OBJS = foo.o \
foobar.o
all: $(OBJS)
$(CC) -shared -o $(SHLIB)$(DLSUFFIX) $(OBJS) -I$(PQINC)
cp *.so $(PGLIB)
clean:
rm -f $(SHLIB) $(OBJS)
The error I get when I run make is:
common.h:58:22: error: postgres.h: No such file or directory
Which suggests that the include path is not being added (the file exists in $PQINC).
Its a long time since I wrote the Makefile - and I haven't written many since. As an aside, I am pretty sure that 'shared' is not the gcc flag to build shared libs on Ubuntu (my current dev box) - I think the flag should be 'fPIC' - can someone confirm this?
I am runing gcc v4.4.3 on Ubuntu 10.0.4 and compiling for use with PG 8.4
Try moving the -I$(PQINC) from target all to the end of line that starts with override CFLAGS.
Placing -Isomething on the compiler line which turns object files, like those in $(OBJS), into executable will have no effect whatsoever.
You need to do it when you compile the source files.
Since your makefile doesn't explicitly show the rule for processing source files, it may well be using a default one, which is incredibly unlikely to know about PQINC.
You seem to be using the default rules to build foo.o from foo.c, which doesn't have your -I. Try adding the following rule to your Makefile:
.c.o:
$(CC) $(CFLAGS) -c $< -o $# -I$(PQINC)