I downloaded the C source code for single-threaded Linux versions of cubist software. what the code does is it takes the input data and generates the regression tree model.
when compiling the source code using Ubuntu terminal it generated the Executable file with out error.
Here is the makefile
CC = gcc -ffloat-store
OFLAGS = -O3
CFLAGS = -DVerbOpt -g -Wall -O0
LFLAGS = $(S)
SHELL = /bin/csh
src =\
global.c\
xval.c\
cubist.c\
sort.c\
construct.c\
predict.c\
stats.c\
discr.c\
rules.c\
contin.c\
formrules.c\
formtree.c\
getdata.c\
getnames.c\
implicitatt.c\
instance.c\
modelfiles.c\
prunetree.c\
regress.c\
trees.c\
update.c\
utility.c
obj =\
global.o cubist.o construct.o\
formtree.o prunetree.o stats.o discr.o contin.o\
trees.o\
formrules.o rules.o\
instance.o\
predict.o\
regress.o\
xval.o\
getnames.o getdata.o implicitatt.o sort.o\
modelfiles.o\
update.o utility.o\
all:
make cubist
$(CC) $(LFLAGS) $(OFLAGS) -o summary summary.c -lm
# debug version (including verbosity option)
cubistdbg:\
$(obj) defns.i extern.i text.i Makefile
$(CC) $(CFLAGS) -o cubistdbg $(obj) -lm
# production version
cubist:\
$(src) defns.i text.i Makefile
cat defns.i $(src)\
| egrep -v 'defns.i|extern.i' >cubistgt.c
$(CC) $(LFLAGS) $(OFLAGS) -o cubist cubistgt.c -lm
strip cubist
rm cubistgt.c
$(obj): Makefile defns.i extern.i text.i
.c.o:
$(CC) $(CFLAGS) -c $<
When i try to do similar work in windows i got error message
$ make all
make cubist
make: /bin/csh: Command not found
make: *** [Makefile:56: all] Error 127
But when i try by removing SHELL = /bin/csh from Makefile it worked. My question here is does it has negative effect on the software or
how could i fix it with out removing SHELL = /bin/csh.
thank you very much
My guess is that by removing the line SHELL = /bin/csh your result is ok.
/bin/csh is a shell (command line interface, command processor, command prompt) used mostly in unix. In your makefile it is defined, but not referenced (not used).
Sometimes makefiles can need a shell (command processor) in order to execute some task, but it is up to the makefile - I mean, the person writing the makefile chooses to use that functionality or not and, if used, can (or must) specify which shell to use. This is not your case, now.
Related
I've written multiple C programs in different files and I want to run all three of them in the same time, on the same argv:
That's what I tried so far but its only running the last program digcmp.c:
CC=gcc
a_OBJS=lexcmp.o
b_OBJS=lencmp.o
c_OBJS=digcmp.o
EXEC=lex len dig
DEBUG = -g
CFLAGS = -std=c99 -Wall -Werror $(DEBUG) #if you have CFLAGS you do not have to write for each file $(CC) -c $*.c!!!
lex: $(b_OBJS)
$(CC) $(a_OBJS) -o $#
len: $(b_OBJS)
$(CC) $(b_OBJS) -o $#
dig: $(c_OBJS)
$(CC) $(c_OBJS) -o $#
lexcmp.o: lexcmp.c
lencmp.o: lencmp.c
digcmp.o: digcmp.c
clean:
rm -f lex $(a_OBJS)
rm -f len $(b_OBJS)
rm -f dig $(c_OBJS)
The make program have many implicit rules. In fact they are what makes your lexcmp.o: lexcmp.c (etc.) rules work.
All you need is to list the rules to make the executable programs themselves:
lexcmp: lexcmp.o
lencmp: lencmp.o
digcmp: digcmp.o
The above is a perfectly fine Makefile on its own, and if you run e.g.
$ make lencmp
then the lencmp.c source file will be built into the object file lencmp.o which will then be linked into the executable lencmp program.
If you want specific compilation flags when building just set the CFLAGS variable and it will be used automatically. I also recommend a default target which might list all executable targets as dependencies to build all of them:
CFLAGS = -Wall -Wextra
.PHONY: all
all: lexcmp lencmp digcmp
This should really be enough to build all your executable files (skipping the object-file intermediate stage) with the flags you want.
The .PHONY target tells make that it's not supposed to generate a file with the name all.
what i'm doing wrong?
And can you send some helpful links to make my work with makefiles easier and better?
get_next_line.o: file not recognized: File format not recognized
collect2: error: ld returned 1 exit status
Makefile:27: recipe for target 'gnl' failed
make: *** [gnl] Error 1
+++
SRC = gnl.c
OBJ = $(SRC:.c=.o)
INCLUDES = gnl.h
NAME = gnl
CFLAGS = -Wall -Werror -Wextra
CC = gcc
DIR = LIBFT
%.o: %.c $(SRC) $(INCLUDES)
$(CC) $(CFLAGS) -c $<
all: $(NAME)
$(NAME): $(OBJ)
make -C $(DIR)
$(CC) $(CFLAGS) -o $(NAME) $(OBJ) -L. $(DIR)/libft.a
clean:
make clean -C $(DIR)
rm -f $(OBJ)
fclean:
make fclean -C $(DIR)
rm -f $(NAME)
re: fclean all
This is not a make error by itself. It says
get_next_line.o: file not recognized: File format not recognized
so that is your problem. Somehow you managed to have a .o file in your directory that is corrupted. Remove it and things will go better.
You have misunderstood the error message. The error message is referring to the file get_next_line.o, not the makefile.
It is the linker (ld) that is reporting the error not make. The command that has failed is that for the target gnl.
It can even be simpler...
It just happened to me with a Makefile.
In the line (in the Makefile) that creates the executable, where there are different names of objects .o, there was a typo. I left the name of the file .cu (CUDA format) instead of .o.
I ran into this error recently, and I have a couple of suggestions that might help. My problem was not a bad .o file, but rather a 32-bit installation rather than a 64-bit installation. If this is the case for you, too, you might get more complete functionality by trying this solution.
In my case, the makefile(s) in question needed different CFLAGS depending on whether the installation was 64-bit or 32-bit. Here are some lines from the README of the project I was trying to make.
By default, the C/C++ software are compiled in 32 bits with the options (-Os) but can be compiled in 64 bits, -m64 is added to the CFLAGS variable in <certain makefiles in the project are listed>
My suggestion is to first try adding -m64 to your CFLAGS. If that doesn't work, delete the -m64 and replace it with -Os.
That is, first try having the following line:
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -m64
Then, from the command line, run
make clean
Followed by whatever make commands you use for your install.
If that doesn't work, change the line in question to
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -Os
Then make clean and the other make stuff.
If some of the C objects are 64-bit and some are 32-bit (I don't know if such a situation actually exists), you might have to do something different.
This worked in my case, details of which you can see here.
Please comment to let me know if it works for you.
[Files in my directory][1]
Need help compiling in a make file.
So I have this link list assignment i'm doing and the directions were.
stringlist.h is supposed to contain the node and the function prototypes
stringlist.c is supposed to have the functions completed that are defined in stringlist.h. BUT stringlist.c is not supposed to contain main at all. Then, namelist.c is supposed to contain main and just have the I/O and its just supposed to call the command functions that are in stringlist.c.
So to compile this we are supposed to create a make file. Whenever I try to I get an error because main doesn't exit in one of the c files. Throughout the term we compiled code like this "gcc -std=gnu99 -m32 -Wall -g -o file file.c"
But it doesn't work.
How would I create the make file? Been spending hours and can't figure it out.
As stated by Jonathan Leffler, the sample Makefile I provided had a few bad ideas. Here's an improvement:
# compiler:
CC = gcc
# compiler flags:
CFLAGS = -g -Wall
# the build target executable:
TARGET = executable
# object files to build:
OBJ = namelist.o stringlist.o
all: $(TARGET)
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ)
Try this:
OBJ := namelist.c stringlist.c
GCC := gcc -g
CFLAGS := -std=gnu99 -m32 -Wall
compile: $(OBJ)
$(GCC) $(CFLAGS) $(OBJ) -o executable
I am in the process of porting some code that was developed in the codeblocks IDE. I am transferring it to a Linux server where I can only use the command line to compile the code. The code is quite large (maybe 100 files) and I need to update the include commands in many files. For when I try to compile it errors on for instance: #include <gsl/gsl_math.h> with a file cannot be found error. I am assuming it cannot be found because the location of the gsl folder was declared in one of the search directory field options in the IDE. I could go through each file an update to the correct path, but is there a better way of doing this for use with a makefile?
Thanks!
EDIT Makefile In Question
# -c : do not link, just create object file
# -o : output file name
CFLAGS += -c -O2 -I../ctraj -I../cspice/include -I../SGP4 -I../cconj -I../GSL-1.13/include
LIBS = -L../ctraj -lctraj -L../cspice/lib -lcspice -L../SGP4 -lsgp4 -L../cconj -lcconj -L./ -lgsl-0 -lgslcblas-0 -lm
DEPS = light.h ../ctraj/ctraj.h ../cconj/cconj.h
OBJ = light.o tle.o propagator.o orbitfit.o conjunction.o light_displacement.o forces_LF.o
OUT = light.exe
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
light: $(OBJ)
cd ../ctraj/; make
gcc -o $(OUT) $(OBJ) $(LIBS)
clean:
rm *.o $(OUT)
Edit 2
Folder Structure
light->(GSL-1.13, Light, cconj, ctraj)
the makefile is inside the Light folder.
Error Message
cd ../ctraj/; make
make[1]: Entering directory `/light/ctraj'
gcc -o forces.o forces.c -c -Wall -Wno-maybe-uninitialized -Wno-unused-but-set-variable -O2 -I../cspice/include -Inrlmsise
In file included from ../Light/../cconj/cconj.h:12:0,
from ../Light/light.h:13,
from forces.c:3:
../Light/../cconj/../GSL-1.13/include/gsl/gsl_blas.h:26:28: fatal error: gsl/gsl_vector.h: No such file or directory
compilation terminated.
make[1]: *** [forces.o] Error 1
make[1]: Leaving directory /light/ctraj'
make: *** [light] Error 2
EDIT 3
Second makefile in cconj
# -c : do not link, just create object file
# -o : output file name
#-L../cconj -lcconj
CFLAGS += -c -O2 -I./ -I../GSL-1.13/include
LIBS = -L./ -lgsl-0 -lgslcblas-0 -lm
INC= -I../GSL-1.13/include
DEPS = cconj.h
OBJ = cconj_util.o ellipse_intersect.o collision_prob_real.o rcs2size.o
OUT = libcconj.a
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
cconj: $(OBJ)
ar rcs $(OUT) $(OBJ)
clean:
rm *.o $(OUT)
Try adding this line to your makefile, and tell us if it works:
CFLAGS += -I../GSL-1.13/include
In order to compile source code and produce object files, Make must use a rule. (If you don't put such a rule in the makefile, Make has a default rule for that purpose.) It looks something like this:
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
Without digging too deeply into how that works, we can say that CFLAGS is a list of arguments to be passed to the compiler. When we add -I../GSL-1.13/include, we tell the compiler "if you want to #include something and can't find it elsewhere, look in ../GSL-1.13/include".
If this approach doesn't work, then there's probably a rule in the makefile we must find and alter.
EDIT:
The problem isn't in this makefile (which already contains a reference to GSL-1.13/include). In this command:
cd ../ctraj/; make
this makefile launches a second Make process, which uses the Makefile in light/cconj/. According to the compiler output (gcc -o forces.o ...), that makefile does not include the reference. So try adding the same line there, and if that doesn't work, post that makefile and we'll keep looking.
Use -I option of gcc to specify where to look for includes.
When we are compiling a C program the output is stored in a.out. How can we redirect the compiled output to another file?
Most C compilers provide an option for this, such as the -o option for gcc and some others:
gcc -o gentext gentext.c
cc -o mainprog -Llib -lmymath firstbit.c secondbit.o
xlc -o coredump coredump.c
-ofilename will make filename instead of a.out.
According to the manual:
-o <file> Place the output into <file>
In Unix, where C originated from, C programs are usually compiled module-by-module, and then the compiled modules are linked into an executable. For a project that consists of modules foo.c and bar.c, the commands would be like this:
cc -c foo.c
cc -c bar.c
cc -o myprog foo.o bar.o
(With -c, the output filename becomes the source file with the suffix replaced with .o.)
This allows you to also re-compile only those modules that have changed, which can be a big time saver for big programs, but can also become pretty tricky. (This part is usually automated using make.)
For a single-module program there's not really any point in first compiling to a .o file, and then linking, so a single command suffices:
cc -o foo foo.c
For single-module programs, it is customary to call the resulting executable program the same as the C source file without the .c suffix. For multi-module programs, there is no hard custom on whether the output is named after the file with the main function or not, so you're free to invent whatever strikes your fancy.
With the -o option.
gcc main.c -o myCoolExecutable.o
This is ok if your program consists of a single file. If you have more files I suggest using make: create a Makefile and then run the command make.
A Makefile is a file containing some rules for compilation.
An example can be the following (# means the line is a comment):
CXX = gcc
#CXXFLAGS = -std=c++11
#INC_PATH = ...
#LIBS = ...
SOURCEDIR := yourSourceFolder
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: yourExecutableName
clean:
$(RM) $(OBJECTS) $(DEPENDS) yourExecutableName
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
yourExecutableName: $(OBJECTS)
$(CXX) $(WARNING) $^ -o $#
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $# $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $#
Shortly CXX variable defines your compiler (gcc, g++), with CXXFLAGS you can define flags for your compilation (i.e. -std=c++11). Then you can include and define custom (INC_PATH and LIBS: not set in the example). With SOURCEDIR you can specify your source code directory (where *.c files are).Then SOURCES is basically telling that the source files for the compilation are all the files having extension *.c.
The Makefile contains a set of rules whose structure is the following:
output: inputs
commandToExecute
The rule to generate your executable file is
yourExecutableName: $(OBJECTS)
$(CXX) $(WARNING) $^ -o $#
which is equivalent to gcc -Wall -Wextra $(OBJECTS) -o yourExecutableName.
$(OBJECTS) are the object file resulting from the compilation. When the above rule is executed, if they are not found make will continue scanning the file to find a rule to generate them. In this case the rule to generate these files is:
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $#
If further information is needed let me know.
If foo will be your executable and bar.c is your source file then the command is:
gcc -o foo bar.c
Compile using:
cc -o <opfilename> <filename.c>
Execute using:
./<opfilename>
gcc filename.c -o outputfile
This command will directly create an outputfile.exe OR outputfile.out according to operating system. In place of filename.c OR outputfile we can enter path, as shown below.
gcc ./home/user/filename.c -o ./home/outputfile
The format of giving the Name of .exe file according to the User Choice in C Language
step 1 :- Run the gcc (or the compiler you have) in the below format on the Terminal
gcc -o put_your_name_you_want_to_give (space) your_file_name_you_want_to_execute
NB:- If you are Running "Vs Code" Use the 'Tab' key for the Auto completion.
step 2 :- Write down the name of the program in format
.\the_name_you_have_given.exe
you are done!
Assuming you are in ubuntu
step-1: run gcc with these commands to compile filename.c
gcc filename.c -o filename.out
filename.out will be created, (it might or might not be shown where the other files are stored)
step-2: execute the filename.out by
./filename.out
step-3: wait for the output
thats it , you are done