Hello!
I want to make Makefile.win which will make a tar.gz with 2 other files(dodaj.c and another Makefile, both are in the same directory where i want use commend make ).My problem is
make dodaj.tar.gz
make: *** No rule to make target 'dodaj.tar.gz'. Stop
Here is my code:
dodaj.tar.gz: dodaj.c Makefile
mkdir dodaj-434686
cp ./dodaj.c ./dodaj-434686
cp ./Makefile ./dodaj-434686
tar -czvf dodaj.tar.gz ./dodaj-43468
rm -rf ./dodaj-434686
Make will look for files named 'makefile' and 'Makefile'. If you are using Gnu make, it will also look for 'GNUmakefile'. It does not look for 'Makefile.win'. To use that file, you must do make -f Makefile.win dodaj.tar.gz
Related
I am following the book "Learn C the Hard Way" and I have reached the section where you compile the code using makefiles. I keep getting errors that the file was not found when running make clean.
Here is the error followed by the make file and the directory
C:\Users\Me\Desktop\C Code\HARD WAY\Dust off that compiler>make clean
rm -f main.c
process_begin: CreateProcess(NULL, rm -f main.c, ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [makefile:7: clean] Error 2
EXECUTABLE=main.exe
CC="C:\Program Files\mingw-w64\x86_64-8.1.0-posix-seh-rt_v6-rev0\mingw64\bin\gcc.exe"
CFLAGS=-Wall -g
clean:
rm -f main
directories
EDIT: I removed the .c from the "rm -f main" as it seems to be a small error but has made no difference to the end result
EDIT 2: I worked out that the make file is issuing linux commands which is why it wasn't working, replacing rm with del fixes the issue
I worked out that the make file is issuing linux commands which is why it wasn't working, replacing rm with del and removing -f fixes the issue
I am learning C and I am trying to call a rule that I have had to write in a makefile:
CFlAGS=-Wall -g
clean:
rm -f ex1
However when I enter the command $make clean I get the error:
make: *** No rule to make target 'clean'. Stop.
I am using Cygwin64 terminal on windows and I have stored the makefile under the name ex2.mak however it is still not working
make looks for the makefile with the name Makefile.
You can use the -f option to tell it to look somewhere else, like so:
make -f ex2.mak clean
or you can rename the makefile to Makefile.
Most beginners' problems with makefiles is: The command (in your case the line containing "rm..." does not begin with a real tab character. If it doesn't, the makefile will not be correctly interpreted.
If you write a makefile, make sure your editor does not convert tabs to spaces and also make sure that you don't type spaces instead of tab characters. Other than that, the makefile looks O.K. to me so far.
I have a small C program that just computes Fibonacci. I have make file to build the file, and when I call make, I get the message make: *** No targets specified and no makefile found. Stop.. If I call make clean, I get make: *** No rule to make target `clean'. Stop. but it seems to see a makeFile (I think). I'm pretty lost and need help.
Here's the text of the make file:
CC=gcc
all: fibonacci
fibonacci: fibonacci.c
$(CC) -pthread -o fib.exe
clean:
rm fib.e xe
rename your makefile to Makefile or use make -f <whatever_name_you_like>. Remember that in unix-like systems file names are often case-sensitive (not in all types of filesystems but in many)
Refer this answer No targets specified and no makefile found
By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile, makefile and Makefile.
You can also try make all and read
What Name to Give Your Makefile
I am writing(at first time) a makefile for my program in C. This is my make file:
CC = gcc
FILES = in_one.c in_two.c in_two.h
OUT_EXE = out_executable
build: $(FILES)
$(CC) -o $(OUT_EXE) $(FILES)
clean:
rm -f *.o core
rebuild: clean build
Actually, everything works properly : Gcc compiler doesn't show any errors, but maybe someone could explain what does these lines mean:
clean:
rm -f *.o core
rebuild: clean build
The clean lines say that if you want to make clean it does not depend on anything (nothing behind ":"). Furthermore the rm command deletes all object files.
The rebuild: clean build says that if you want to make rebuild it depends on clean and build. So the first thing to do is clean (= delete all object files) and then make build (= compile all source files). After that there is nothing more to do so make stops.
For a quick start, make recipes have the following syntax:
target: dependency1 dependency2 ... dependencyN
command1
command2
...
command3
So if target needs to be made at first all dependencies (dependency1 - dependencyN) are made. After this is done command1 - commandN are executed in that order.
You are rm (removing) or deleting all (*) the existing .o Files. So the next time you compile or call the make file you are just left with the new ones.
Build: $(Files) is creating the .o so the compiler can link them together into an executable
I've just started to learn C (using Thinking In C) and I'm wondering about what files I should be ignoring in a C project's git repository.
No suggestion can be too obvious -- I'm a total noob. Thanks!
I guess there will be a few generated files that you don't wan't to be sticking in your repo (assuming your build output dir is in your git heirachy):
object files (.o, o.obj)
libraries (.lib)
DLLs, shared objects (.so, .dll)
Executables (.exe, a.out ?)
GIT ignore files are something I tend to do iteratively. "Hey, I don't need those things in my repo" ...
Edit: re dmckee's comment
Yep, you definately want to be ignoring swap files, temp files etc. I have the following as a baseline for my .gitignore:
*.swp
.~
thumbs.db
You can also setup your build to happen in a subdirectory say build and then you can ignore the whole thing inside .gitignore
build/
And you're done.
I use this in my .gitignore
But I am building for micro-controllers, so I don't know if it helps you much.
The easiest way to know, is just do a make clean, then add all your files, then do a make all and see what extra stuff appears.
#Some of these are related to eclipse. So i keep them out of my repo
.cproject
.dep/
.project
.settings/
#files being edited
*~
# make and build files
*.lst
*.o
*.eep
*.lss
*.map
*.sym
# I keep these, since I prefer having the reference of the final build
# *.elf
# *.hex
Github's .gitignore file templates cover most of the common files for projects in a variety of languages.
The C .gitignore template looks like this:
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf
Using a *nix system and a Makefile, you could add each generated file to .gitignore.
As an example I use the following when creating an executable from a single source (Example for a C executable generation):
%: %.c
gcc -o $# $<
grep '^$#$$' .gitignore > /dev/null || echo '$#' >> .gitignore
The following line can be added to other recipes to add target $# to .gitignore file:
grep '^$#$$' .gitignore > /dev/null || echo '$#' >> .gitignore
Explanation:
grep '^$#$$' .gitignore : searches for the target in .gitignore
^ indicates start of line
$$ is a single $ (but Makefile needs $$ to work) and indicates the end of the line
'^$#$$' represents the target name
|| : executes the next command only if the left hand one failed
so only if grep ... does not find the target name in .gitignore, echo ... is executed
echo '$#' >> .gitignore: adds the target name to .gitignore
Eventually, you will add to clean and rebuild everything to make sure all files are correctly ignored