I am trying to use make with my c program. It's a simple calculator program. I created the makefile but it is not being executed when i run make using the terminal.
here is my make file
calculatormade:
\tadd.o sub.o multiply.o divide.o Calculator_Main.o gcc add.o sub.o multiply.o divide.o Calculator_Main.o -o calculatormade
add.o:
\tadd.c gcc add.c -c
sub.o:
\tsub.c gcc sub.c -c
multiply.o:
\tmultiply.c gcc multiply.c -c
divide.o:
\tdivide.c gcc divide.c -c
Calculator_Main.o:
\tCalculator_Main.c head.h gcc Calculator_Main.c -c
clean:
\trm calculatormade add.o sub.o multiply.o divide.o Calculator_Main.o
The tab separator is misplaced. You should put on the first line the taget, colon and the files it is dependent on.
On the second line (that must start with tab) you need to build the build instructions. For exmple:
calculatormade: add.o sub.o multiply.o divide.o Calculator_Main.o
<TAB>gcc add.o sub.o multiply.o divide.o Calculator_Main.o -o calculatormade
add.o: add.c
<TAB>gcc add.c -c
Related
I'm trying to compile a simple project with .c and .s files using my Mac.
When I run 'make' it goes threw on the compilation, and I think it failed when its trying to link (not sure).
Here is the error it shows:
gcc -m32 -g -Wall -c -o main.o main.c
gcc -m32 -g -Wall -c -o numbers.o numbers.c
nasm -g -f macho -w+all -o add.o add.s
gcc -m32 -g -Wall -o run main.o numbers.o add.o
ld: malformed file
/Library/Developer/CommandLineTools/SDKs/MacOSX10.14.sdk/usr/lib/libSystem.tbd:4:18: error: unknown enumerated scalar
platform: zippered
^~~~~~~~
file '/Library/Developer/CommandLineTools/SDKs/MacOSX10.14.sdk/usr/lib/libSystem.tbd'
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [run] Error 1
and I'll add the makefile as well:
run: main.o numbers.o add.o
gcc -m32 -g -Wall -o run main.o numbers.o add.o
main.o: main.c
gcc -m32 -g -Wall -c -o main.o main.c
numbers.o: numbers.c
gcc -m32 -g -Wall -c -o numbers.o numbers.c
add.o: add.s
nasm -g -f macho -w+all -o add.o add.s
.PHONY: clean
clean:
rm -f *.o run
Is it possible to make two files in a single makefile? Essentially a program and a programtest. I have seen other answers, but their syntax went completely over my head. Right now my Makefile only makes one of the programs, and I cant figure out how to have it make both
Would it be possible for someone to provide a template for how a Makefile would be structured to compile two programs?
all: main test
test: objects/Math.o objects/Stack.o objects/Queue.o objects/myUnitTesting.o objects/test.o
gcc objects/test.o objects/Math.o objects/Stack.o objects/Queue.o objects/myUnitTesting -o test
main: objects/Stack.o objects/Queue.o objects/Math.o objects/Point.o objects/main.o
gcc objects/main.o objects/Stack.o objects/Queue.o objects/Point.o objects/Math.o -o main
objects/test.o: test.c
gcc -g -Wall -O -c -o objects/test.o test.c
objects/main.o: main.c
gcc -g -Wall -O -c -o objects/main.o main.c
objects/myUnitTesting.o: cs/myUnitTesting.c
gcc -g -Wall -O -c -o objects/myUnitTesting cs/myUnitTesting.c
objects/Math.o: cs/Math.c
gcc -g -Wall -O -c -o objects/Math.o cs/Math.c
objects/Stack.o: cs/Stack.c
gcc -g -Wall -O -c -o objects/Stack.o cs/Stack.c
objects/Queue.o: cs/Queue.c
gcc -g -Wall -O -c -o objects/Queue.o cs/Queue.c
objects/Point.o: cs/Point.c
gcc -g -Wall -O -c -o objects/Point.o cs/Point.c
clean:
rm -f objects/*o main
Then you only need to type:
make all
and it is going to compile your main.c and test.c files
You can multiple exes in one makefile, here is sample for building 2,
you need to do make all to build
prog1: prog1.o
gcc prog1.o -o prog1 2>>compile.log 1>&2
prog2: prog2.o
gcc prog2.o -o prog2 2>>compile.log 1>&2
all: prog1 prog2
.c.o:
gcc -o $# -c $*.c 2>>compile.log 1>&2
Here is a scenario where 2 targets are main1 and main2.
TARGET1 = main1
TARGET2 = main2
$(TARGET1): main1.o
gcc main1.o -o $#
$(TARGET2): main2.o
gcc main2.o -o $#
%.o: %.c
gcc -c $< -o $#
run1: $(TARGET1)
./$(TARGET1)
run2: $(TARGET2)
./$(TARGET2)
all: $(TARGET1) $(TARGET2)
./$(TARGET1)
./$(TARGET2)
Remember that the indentation is a <tab> character, not space characters.
The following command will compile and run main1 executable.
make run1
The following command will compile and run main2 executable.
make run2
The following command will compile and run main1 executable followed by main2 executable.
make all
It is possible.
Here is a simpler version of the Makefile:
all: program programtest
program:
gcc -o program program.c
programtest:
gcc -o programtest programtest.c
Then you just have to type make:
$ make
gcc -o program program.c
gcc -o programtest programtest.c
Here is my my makefile. I know there is a shorter way to write it out, but I have a question on how to run it. My hw says I have to use the command: make run --- this command should cause the executable file to run using file redirection to read the input file data.
How would I go about setting that up?
Also i know the gcc is supposed to be tabbed.
test: main.o sum.o stack.o bSearch.o database.o db.o set.o parse.o bubble.o
gcc -o object main.o sum.o stack.o bSearch.o db.o set.o parse.o bubble.o
main.o: main.c sum.h
gcc -c main.c
sum.o: sum.c sum.h
gcc -c sum.c
stack.o: stack.c stack.h
gcc -c stack.c
bSearch.o: bSearch.c defs.h sortAndsearch.h
gcc -c bSearch.c
database.o: database.c defs.h parse.h
gcc -c database.c
db.o: db.c defs.h
gcc -c db.c
set.o: set.c set.h db.h
gcc -c set.c
parse.o: parse.c parse.h
gcc -c parse.c
bubble.o: bubble.c defs.h
gcc -c bubble.c
sortAndsearch.h: db.h
defs.h: set.h sortAndsearch.h
stack.h: set.h
clean:
rm *.o object
"run" is just like any other target in your Makefile such as "test" or "set.o" - but you have to add the rule to the Makefile for make to know what to do with it.
run:
./test < input.txt
What I want to know is how to write a makefile that compiles a program and then removes the object files created in the process with just using command 'make' so I don't have to run command 'make clean' afterwards. Here's my current makefile:
prog: prog.o prog_func.o
gcc prog.o prog_func.o -o prog -Wall -std=c99
prog.o: prog.c prog_func.h
gcc prog.c -c -Wall -std=c99
prog_func.o: prog_func.c prog_func.h
gcc prog_func.c -c -Wall -std=c99
clean:
rm prog.o prog_func.o
EDIT:
And this is how it's done:
prog: prog.o prog_func.o
gcc prog.o prog_func.o -o prog -Wall -std=c99
rm prog.o prog_func.o
prog.o: prog.c prog_func.h
gcc prog.c -c -Wall -std=c99
prog_func.o: prog_func.c prog_func.h
gcc prog_func.c -c -Wall -std=c99
It works now. Thanks for quick responses.
After building executable, you just give the same command (rm command) after the executable command
How about compile without making f files like this
gcc -Wall -o prog prog.c
this command will not produce o files.
I have just taken a sample example.
makebuild: clean prog
prog:
gcc a.c -o a.o
clean:
rm a.o
Running 'make' from command line will first 'rm' a.o file and then run 'gcc a.c -o a.o'. The only problem here is that it will not work for first time as makebuild is calling clean first and it will throw an error as it will not find a.o file. You have to put check that 'rm' only when a.o file is present.
something like this:
clean:
if a.o exist
rm a.o
I know this error has been beaten to death, but I cannot seem to get it to work. I have linked my makefile below:
all: gensine info cs229towav
encode.o: encode.h encode.c
gcc -c encode.c
write.o: write.c write.h
gcc -c write.c
gensine.o: encode.c gensine.h gensine.c helper.c write.c
gcc -c gensine.c -lm
helper.o: helper.c helper.h
gcc -c helper.c
read.o: read.h read.c
gcc -c read.c
info.o:read.c info.h info.c decode.c
gcc -c info.c
decode.o: decode.c decode.h helper.c
gcc -c decode.c
cs229towav.o: write.c read.c cs229towav.c cs229towav.h helper.c decode.c encode.c
gcc -c cs229towav.c -lm
gensine: encode.o gensine.o write.o helper.o
gcc -o gensine encode.o gensine.o write.o helper.o -lm
info: read.o info.o decode.o helper.o
gcc read.o info.o decode.o helper.o
cs229towav: write.o read.o cs229towav.o decode.o encode.o helper.o
gcc -o write.o read.o cs229towav.o decode.o encode.o helper.o -lm
Clean:
rm -rf *o gensine info cs229towav
When I run a command such as "make gensine" I am returned with the following result:
>cc gensine.c -o gensine
/tmp/ccojm09X.o: In function `encodeCsFormat':
gensine.c:(.text+0x4b1): undefined reference to `sin'
/tmp/ccojm09X.o: In function `encodeWavFormat':
gensine.c:(.text+0xa39): undefined reference to `sin'
collect2: error: ld returned 1 exit status
After reading this is says undefined reference to sin, which is with the math library. Those functions listed are in the "encode.c" file which are included in the "gensine.c" file.
The command in the makefile:
gcc -o gensine encode.o gensine.o write.o helper.o -lm
does not match the command you printed at the end:
cc gensine.c -o gensine
Notice also that there is no -lm
Note that make knows how to make object files so you don't need most of the makefile. Try this (remember to indent with TABs):
.PHONY : all clean
all = gensine info
CFLAGS =-Wall
LIBS = -lm
gensine: encode.o gensine.o write.o helper.o
gcc -o $# $^ $(LIBS)
info: read.o info.o decode.o helper.o
gcc -o $# $^ $(LIBS)
cs229towav: write.o read.o cs229towav.o decode.o encode.o helper.o
gcc -o $# $^ $(LIBS)
clean:
rm -rf *.o gensine info cs229towav
Edit:
Boddie, note that your confusion arose because you thought the makefile was a script - ie. that you were running your script named make when you typed make gensine. In fact make is a command like gcc somewhere else in the filesystem (on Linux etc, type which make to see where it is). The make command expects to find an input file containing build rules called makefile or Makefile in the current directory. If it doesn't find that file it uses some built-in rules instead - hence the cc gensine.c -o gensine which is nowhere in your makefile. If you want to, you can tell make the name of the makefile (so that it doesn't use the default names) with the -f switch, as #DanielFischer described in the comments.