I have a project that contains 4 source files :
RTP.c, RTCP.c RTSP.c main.c
and 3 header files :
RTP.h RTCP.h RTSP.h
I have to include all the header files in the main and the RTCP.h in the RTP.c after I included the header files in the source files I linked them in a make file please help me understand the problem.
the RTP.c
#include "RTP.h"
#include "RTCP.h"
the RTCP.c
#include "RTCP.h"
The RTSP.c
#include "RTSP.h"
The main.c
#include "RTP.h"
#include "RTSP.h"
The make file:
OBJS = main.o RTPfunctions.o RTCPfunctions.o RTSPfunctions.o
CC = gcc
CCFLAGS = -g
Client : $(OBJS)
$(CC) $(OBJS) -o -pthread client
RTCPfunctions.o : RTCPfunctions.c RTCPfunctions.h
$(CC) -c -g -pthread RTCPfunctions.c
RTSPfunctions.o : RTSPfunctions.c RTSPfunctions.h
$(CC) -c -g -pthread RTSPfunctions.c
RTPfunctions.o : RTPfunctions.c RTPfunctions.h RTCPfunctions.h
$(CC) -c -g -o -pthread RTPfunctions.c RTCPfunctions.o
main.o : main.c RTPfunctions.h RTSPfunctions.h
$(CC) -c -g -o -pthread main.c RTPfunctions.o RTSPfunctions.o
clean:
\rm *.o *~ client
Your question is not very verbose, however, from a quick glance at your makefile, we can say, as per the online gcc manual,
-o file
Place output in file file. This applies to whatever sort of output is being produced, whether it be an executable file, an object file, an assembler file or preprocessed C code.
Basically, this says, the immidiate next argument to -o should be the output file name.
Also, to follow the order of linking, the pthread library should be placed at the end, like
$(CC) $(OBJS) -o client -pthread
Related
In a program, I have a list.c file, list.h file and run.c file. In the run.c file, the code contains my main program and also "#include list.h". In my list.h file, my functions are just void and being defined. Finally, in my list.c file, I include list.h again and I have the meaning and code of what each function is going to do. I made a makefile that looks like so:
SOURCES = run.c list.c
OBJECTS= run.o list.o
HEADERS = list.h
CC = gcc
CFLAGS = -g -Wall
lab1: $(OBJECTS)
(tab) $(CC) $(CFLAGS) $(OBJECTS) -o lab1
clean:
(tab) rm -fR *o lab1
There is nothing wrong in any of my code because it is already finished and I am just copying code. However, I am unsure how to use the makefile to run these multiple files. I am only familiar with runner files after compiling with gcc and using "./". Is there something wrong with my makefile or is there a step for compiling these files in a different way?
Thank you for any help
The given makefile is working and generates an executable lab1 file. However, the .o files depend on the list.h file, and this dependency is not captured.
You should specify targets to build the .o files, as follows:
SOURCES = run.c list.c
OBJECTS= run.o list.o
HEADERS = list.h
CC = gcc
CFLAGS = -g -Wall
lab1: $(OBJECTS)
(tab) $(CC) $(CFLAGS) $(OBJECTS) -o lab1
%.o: %.c $(HEADERS)
$(CC) -c $(CFLAGS) $< -o $#
clean:
rm -fR *o lab1
Word of caution: With this makefile, if the list of HEADERS grows, a change in any of the headers will warrant a rebuild of all .o files.
For example, imagine we also have buf.c which uses buf.h. Now HEADERS = list.h buf.h. If we change buf.h, our makefile would rebuild both list.o and buf.o, even though a buf.o rebuild would suffice.
To remedy this, we could use a more verbose makefile which identifies the specific header prerequisites for each .o file with rules such as the following:
list.o: list.c list.h
$(CC) -c $(CFLAGS) $< -o $#
buf.o: buf.c buf.h
$(CC) -c $(CFLAGS) $< -o $#
Solution 1: Simply list each .c file separately as input and compile once
gcc list.c run.c -o lab1
Solution 2: Compile each .c file separately
gcc -c list.c
gcc -c run.c
gcc -o lab1 list.o run.o
Your project is small and simple enough that a fully generalized makefile is overkill:
SOURCES = run.c list.c
CC = gcc
CFLAGS = -g -Wall
all:
$(CC) $(CFLAGS) $(SOURCES) -o lab1
clean:
rm -fR *o lab1
The all: is a default target that executes when you simply type make with no arguments.
After compiling, it did end up making a lab1 file that I could run and everything worked. My makefile ended up working fine, I was just completely oblivious to the fact that it was making a file called lab1. I did change my makefile to the above options and that also worked. Thank you
Here is my header file
#include <stdio.h>
#include <stdlib.h>
#include "gd.h"
#include "gdfontmb.h"
#include "gdfontl.h"
#include "gdfontg.h"
When I run this program I usually type 'gcc -o test test.o -lm -lpng -lgd'
It works fine for only one .c file, but this is just for testing. I want to link this with others c file in my project (Actually I'm really new to use gd.h)
Here is my Makefile (but It isn't work!!)
ifeq ($(OSTYPE),WINDOWS)
EXECEXT =.exe
COMP =__MINGCC__
PLATFORM =mingw
else
EXECEXT =
COMP =__GCC__
PLATFORM =linux
endif
EXECUTABLES= test$(EXECEXT)
all : $(EXECUTABLES)
test.o : test.c
gcc -c test.c
test$(EXECEXT) : test.o
gcc -o test$(EXECEXT) test.o -lm -lpng -gd
clean :
-rm *.o
-rm $(EXECUTABLES)
Using this Makefile, I got all error about undefined reference to whatever that are in the gd library.
What did I do wrong and How can I fix this?
Your own cc command already gives the answer. You need -lgd, not -gd.
E.g. set in the start:
LIBS=-lm -lpng -lgd
CC=gcc
(the latter can be the full OS-dependent path as well, and then the CC should be part of the OS specific part, and be specified as a full path).
and change the gcc line later to
$(CC) -o test$(EXECEXT) test.o $(LIBS)
And the rule for test.o is (usually) not really needed, as it is a default way to make a .o file from a .c file.
I have to compile a client.c file; in this file there are macro defined in utiliy_lib.h
When I run :
gcc -Wall -c client.c utility_lib.h
The compiler doesn't find macro definitions.
I have this file in the same folder "code":
client.c
server.c
utility_lib.c //it contains generic macro using by every file
utility.c //it contains utility function, used by client and server
msg_queue.c // it contains function to manipulate message queue (this is a little project for a chatroom)
send_receive.c //it contains function to send and receive message
the makefile that I tried is:
CC = gcc -Wall -O0 -g
LDFLAGS = -lpthread
ARCH = $(shell uname -m)
all: client server
server: common.h main.c msg_queue.c send_recv.c util.c
rm -f build/*.o
$(CC) -c main.c -o build/main.o
$(CC) -c send_recv.c -o build/send_recv.o
$(CC) -c util.c -o build/util.o
$(CC) -c msg_queue.c -o build/msg_queue.o
$(CC) -o server build/*.o $(LDFLAGS)
client:
ln -s -f client-$(ARCH) client
:phony
clean:
rm -f client server build/*.o
Anyone could help me please?
Client.C needs to
#include "utility_lib.h"
Near the top of the file
That gives it the definitions
Then compile is
gcc -Wall -c client.c
I'm using gcrypt, but my compiler seems to unable to find it. Here is my makefile. function.c is a function source file containing functions I defined; I also wrote a header file miao.h with function declaration, and gcrypt.h is included in it. main.c is a source file including miao.h. When I do make: .Could anyone help me? This bothers me so long.
CC = gcc
CFLAGS = 'libgcrypt-config --cflags'
LIBS = 'libgcrypt-config --libs'
OBJS = function.o main.o main
all: $(OBJS)
function.o: function.c
$(CC) -c function.c $(CFLAGS)
main.o: main.c
$(CC) -c main.c $(CFLAGS)
main: main.o function.o
$(CC) -o main main.o function.o $(LIBS)
clean:
rm $(OBJS)
the makefile should be written more like the following:
caveat: I was unable to test the makefile as I do not have libgcrypt-config available.
Per the web site: https://gnupg.org/documentation/manuals/gcrypt/Building-sources.html the libgcrypt-config is an executable so should be surrounded by back-ticks, not single quotes so it will be executed in the current shell.
(back ticks on stackoverflow will result in emphasised text but should still be visible as to where they should be placed.)
Note: where I have placed <tab> your actual makefile needs to have a tab character
Note: targets, like all and clean do not produce a file with the same name, so early in the file there needs to be the statement: .PHONY: all clean
when defining a macro, use := rather than = so the macro is only evaluated once.
Any calls to shell functions should be incorporated via a macro, so it is easy to make a change. In general it is best to include the path to the shell function: I wrote this on Linux, your path may be different. Specifying the actual path becomes very important when cross compiling or there are duplicate names visible via the $PATH statement (as can easily be the case with gcc)
Note: the actual libgcrypt-config executable must be in visible via your $PATH environment variable.
Note: all the individual compile statements could be reduced to the following two lines: (and nothing else needed for the compiles)
%.o: %.c
<tab>$(CC) -c $< -o $# -I. $(CFLAGS)
Note: do not place the contents of a rule where the dependencies is expected. This error was noted in the clean: target
the proposed makefile follows:
CC := /usr/bin/gcc
RM := /usr/bin/rm
CFLAGS := `libgcrypt-config --cflags`
LIBS := `libgcrypt-config --libs`
OBJS := function.o main.o main
TARGET := main
.PHONY: all clean
all: $(TARGET)
function.o: function.c
<tab>$(CC) -c function.c $(CFLAGS) -o function.o -I.
main.o: main.c
<tab>$(CC) -c main.c $(CFLAGS) -o main.o -I.
$(TARGET): $(OBJS)
<tab>$(CC) -o $(TARGET) $(OBJS) $(LIBS)
clean:
<tab>$(RM) -f $(OBJS)
I need to create a makefile for an assignment I need to run on Linux. I have no idea how to write makefiles.
The structure of the project is as follows:
Logic.h
Max.h which includes Logic using a header guard in the following way:
#ifndef _GUI
#include "Logic.h"
#endif
GUI.h which includes max.h and logic.h in the following way:
#ifndef _GUI
#define _GUI
#include "Logic.h"
#include "Minimax.h"
#endif
prog.h which includes GUI.h (prog is the main file - the main function is there)
All the header files have corresponding .c files that include only their respective header.
GUI.h uses SDL 1.2 so it includes also the following
#include "SDL.h"
#include "SDL_video.h"
I understand that special flags have to be inserted to the makefile so the SDL can run properly.
This is an example of a makefile that includes only one SDL file so it has the flags for sdl and the flags they require for notifying about errors and warnings:
all: sdl_test
clean:
-rm sdl_test.o sdl_test
sdl_test: sdl_test.o
gcc -o sdl_test sdl_test.o -lm -std=c99 -pedantic-errors -g `sdl-config --libs`
sdl_test.o: sdl_test.c
gcc -std=c99 -pedantic-errors -c -Wall -g -lm sdl_test.c `sdl-config --cflags`
But I don't know how to create a makefile for this file (project) structure, and where to put the SDL flag - only for the files that have SDL, or only the file that have SDL and include files that have SDL or all files.
This is a simple example
OBJECTS = sdl_test.o # add more files just separated by spaces -> filename.o
LDFLAGS = -lm `sdl-config --libs`
CFLAGS = -Wall -Werror -pedantic -g3 -O0 # full debugging on
CC = gcc
TARGET = sdl_test
all:
$(CC) -o $(TARGET) $(OBJECTS) $(LDFLAGS)
clean:
#rm $(OBJECTS) $(TARGET)
%.o: %.c
$(CC) $(CFLAGS) -c $<
Don't copy and paste because Makfiles require tabs for indentation.
A quick and dirty Makefile (i.e., one you don't really want to distribute for a finished product) could be just
SRCS = Max.c GUI.c prog.c
OBJS := $(patsubst %.c, %.o, $(SRCS))
.PHONY: all clean
.DEFAULT_GOAL = all
all: sdl_test
clean:
-rm $(OBJS) sdl_test
sdl_test: $(OBJS)
gcc -o $# $^ -lm -std=c99 -pedantic-errors -g `sdl-config --libs`
%.o: %.c
gcc -std=c99 -pedantic-errors -c -Wall -g -lm $< `sdl-config --cflags`
See Make automatic variables for details, but briefly the special make variables mean
$# - the thing that comes before the colon
$< - the first thing that comes after the colon
$^ - everything that comes after the colon