I have the following error
make all
Building file: ../src/asm.S
Invoking: GCC Assembler
arm-linux-gnueabi-as -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -ftree- vectorize -o "src/asm.o" "../src/asm.S"
arm-linux-gnueabi-as: unrecognized option '-tree-vectorize'
make: *** [src/asm.o] Error 1
while compiling FFMpeg code for fourier transform code using .S files which include VFP commands
the options used in compiler:
Commands in Build C/C++ settings section
GCC C Compiler :
arm-linux-gnueabi-gcc -O3 -S -mcpu=cortex-a8 -mfpu=neon -ffast-math -mfloat-abi=softfp
GCC C Linker:
arm-linux-gnueabi-gcc -mcpu=cortex-a8 -mfpu=neon -ffast-math -ftree-vectorize -mthumb -mfloat-abi=softfp
GCC Assembler
arm-linux-gnueabi-as -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize
I am using Eclipse.
Thanks in advance for your help.
Mahmoud
-ftree- vectorize is a gcc option used for automatic vectorization of C and C++ code. You shouldn't (can't) use it on as.
Related
I'm trying to cross-compile an llvm-ir file to assembly, or better generate an object file, for an ARM Cortex M4 microprocessor using llc compiler.
Which are the parameters that I have to specify in order to do so?
I have tried with this command
llc -mtriple=armv7m-eabi -mcpu=cortex-m4 file.ll -o file.s
It doesn't throw any error but the assembly code generated is still for an x86 machine.
In particular, trying to compiling with random parameters, e.g.
llc -mtriple=randomwords -mcpu=cortex-m4 file.ll -o file.s
It goes smooth, producing an assembly code for the x86 machine. It ignores what I specify.
I found a solution, or better a work around to this problem.
Instead of using directly llc, first I've obtained the binary code through this command
llvm-as file.ll -o file.bc
An than I used clang to crosscompile and obtain the object file for ARM Cortex M4 using this instruction
clang --target=arm-none-eabi -march=armv7e-m -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -nostdlib file.bc -c -o file.o
The -c is used to compile only.
It is also possible to obtain the assembly code by using the following command line
clang -S --target=arm-none-eabi -march=armv7e-m -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -nostdlib file.bc -o file.s
llc (not sure about prior to v9) seems to only care about the architecture.
I can cross compile and link with the following script (for a RPI running Linux):
#/bin/sh
llc-9 -march=arm -float-abi=hard -O3 -filetype obj $1.ll -o $1.o
~/devel/musl/musl-cross-make/output/bin/arm-linux-musleabihf-gcc -mfloat-abi=hard -static $1.o -o $1
llc --version will show the available architectures
Try the following for your case (or use a more specific architecture if it is in the list):
llc -march=arm -mcpu=cortex-m4 -filetype obj file.ll -o file.o
I have a DE1-SoC (Cyclone V) board where I am trying to get timer interrupts to work on the HPS. I found an example in the Intel FPGA University Program called "interrupt_example", and when I run it on the Intel FPGA Universioty Program, it runs perfectly.
Now I want to transfer this project to ARM DS, but I cannot get it to work because everytime when I am trying to write to the interval timer at address 0xFF202000, the debugger won't proceed. When I try to look in the memory of 0xFF202000 in ARM DS, I also cannot see anything.
I am using the same compiler (GCC C 4.7.3 arm-altera-eabi) and I tried to use the same compiler arguments:
Intel FPGA Monitor Program
rm -f interrupt_example.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 interrupt_example.c -o interrupt_example.c.o
rm -f exceptions.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 exceptions.c -o exceptions.c.o
rm -f HPS_timer_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 HPS_timer_ISR.c -o HPS_timer_ISR.c.o
rm -f interval_timer_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 interval_timer_ISR.c -o interval_timer_ISR.c.o
rm -f pushbutton_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 pushbutton_ISR.c -o pushbutton_ISR.c.o
rm -f interrupt_example.axf
ARM DS
make all
'Building file: ../interrupt_example/HPS_timer_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/HPS_timer_ISR.d" -MT"interrupt_example/HPS_timer_ISR.o" -c -o "interrupt_example/HPS_timer_ISR.o" "../interrupt_example/HPS_timer_ISR.c"
'Finished building: ../interrupt_example/HPS_timer_ISR.c'
' '
'Building file: ../interrupt_example/exceptions.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/exceptions.d" -MT"interrupt_example/exceptions.o" -c -o "interrupt_example/exceptions.o" "../interrupt_example/exceptions.c"
'Finished building: ../interrupt_example/exceptions.c'
' '
'Building file: ../interrupt_example/interval_timer_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/interval_timer_ISR.d" -MT"interrupt_example/interval_timer_ISR.o" -c -o "interrupt_example/interval_timer_ISR.o" "../interrupt_example/interval_timer_ISR.c"
'Finished building: ../interrupt_example/interval_timer_ISR.c'
' '
'Building file: ../interrupt_example/pushbutton_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/pushbutton_ISR.d" -MT"interrupt_example/pushbutton_ISR.o" -c -o "interrupt_example/pushbutton_ISR.o" "../interrupt_example/pushbutton_ISR.c"
'Finished building: ../interrupt_example/pushbutton_ISR.c'
' '
'Building file: ../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF".metadata/.plugins/org.eclipse.cdt.make.core/specs.d" -MT".metadata/.plugins/org.eclipse.cdt.make.core/specs.o" -c -o ".metadata/.plugins/org.eclipse.cdt.make.core/specs.o" "../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c"
'Finished building: ../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c'
' '
'Building file: ../main.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"main.d" -MT"main.o" -c -o "main.o" "../main.c"
'Finished building: ../main.c'
' '
I am also using the same linker arguments:
Intel FPGA Monitor Program
arm-altera-eabi-gcc -Wl,--defsym -Wl,arm_program_mem=0x40 -Wl,--defsym -Wl,arm_available_mem_size=0x3fffffb8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -Wl,--section-start -Wl,.vectors=0x0 -T"C:/intelFPGA_lite/17.0/University_Program/Monitor_Program/build/altera-socfpga-hosted-with-vectors.ld" interrupt_example.c.o exceptions.c.o HPS_timer_ISR.c.o interval_timer_ISR.c.o pushbutton_ISR.c.o -o interrupt_example.axf
ARM DS
arm-altera-eabi-gcc -T "C:\intelFPGA_lite\17.0\University_Program\Monitor_Program\build\altera-socfpga-hosted-with-vectors.ld" --exceptions -Wl,--defsym -Wl,arm_program_mem=0x40 -Wl,--defsym -Wl,arm_available_mem_size=0x3fffffb8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -Wl,--section-start -Wl,.vectors=0x0 -o "Baremetal_Hex_Disco.axf" ./interrupt_example/HPS_timer_ISR.o ./interrupt_example/exceptions.o ./interrupt_example/interval_timer_ISR.o ./interrupt_example/pushbutton_ISR.o ./.metadata/.plugins/org.eclipse.cdt.make.core/specs.o ./main.o
I also tried to use the same preloader, but this does not work out when I am writing the debug script. I am not sure if this is the problem. If this is actually the problem, I would appreciate it if someone can help me writing another debug script, because ARM DS is giving me problems when I try to use u-boot-spl.de1-soc.srec as a preloader.
Preloader information in Intel FPGA Monitor Program
Info: Running Quartus Prime Programmer
Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
Info: Copyright (C) 2017 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Sun Feb 07 10:04:39 2021
Info: Command: quartus_hps --cable="DE-SoC [USB-1]" -o GDBSERVER --gdbport0=3350 --preloader=C:/intelFPGA_lite/17.0/University_Program/Monitor_Program/arm_tools/u-boot-spl.de1-soc.srec --preloaderaddr=0xffff13a0 --source=C:/Users/red25/Documents/interrupt_example.srec
Current hardware is: DE-SoC [USB-1]
Successfully change hardware frequency to 16Mhz
Found HPS at device 1
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
AHB Port is located at port 0
APB Port is located at port 1
Double check device identification ...
>>CPU0 halted at 0x2fa8.
>>Resetting HPS.
>>Downloading preloader.....
>>Program loaded. PC set to program entry (0xFFFF0000)
>>Setting vector base address register to: 0xffff0000
>>Running preloader..
>>Preloader successfully run.
>>Downloading user program.
>>Program loaded. PC set to program entry (0x0128)
>>Setting vector base address register to: 0x0
>> Hard breakpoint set.
Starting GDB Server.
Debug script in ARM DS
reset
wait 5s
stop
wait
loadfile "$sdir/../../preloader/uboot-socfpga/spl/u-boot-spl" 0x0
set semihosting enabled true
delete
tbreak spl_boot_device
run
wait
loadfile "$sdir/../Debug/Baremetal_Hex_Disco.axf" 0x0
start*
The disassembly of the code where the 0xFF202000 is being written also looks identical:
Intel FPGA Monitor Program
Disassembly picture Intel FPGA Monitor Program
ARM DS
Disassembly picture ARM DS
I tried everything which I could think of now. I really hope someone can help me. Thank you in advance.
Edit:
In the mean time, I found that when the program tries to write to 0xFF202000, it enters an endless loop in assembly. I am not really familiar with assembly, so I am not sure why this happens.
Endless loop assembly 0xFF202000
I am not familiar with OS X at all, and I need to compile a C file. Here is the code I use in Linux. What is the OS X version of those?
gcc -m64 -std=gnu99 -I/usr/include/R -DNDEBUG -I/usr/local/include -fpic -O2 -g -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector-strong --param=ssp-buffer-size=4 -grecord-gcc-switches -m64 -mtune=generic -c myfile.c -o myfile.o
gcc -m64 -std=gnu99 -shared -L/usr/lib64/R/lib -Wl,-z,relro -o myfile.so myfile.o -L/usr/lib64/R/lib -lR
Thanks!
You need to install Xcode, which is free, and will allow you to install gcc just by typing gcc in Terminal. From there on, you can just compile .c files using it. Also, you might want to just type gcc myfile.c -o myfile instead of adding all of those flags, because the OS X filesystem hiearchy is different from that of Linux, and adding those extra flags might make the command not work.
this is driving me bonkers.
For parallel make builds (-j), you're supposed to be able to synchronize the console output. Here is ref:
GNU Make Manual: 5.4.1 Output During Parallel Execution
I'm using GNU Make 3.82 for x86_64-redhat-linux-gnu
Un-Synchronized:
make -j8 all //not synchronized
yields (i'm using eclipse-cdt managedbuild here):
Building file: ../dome.c
Building file: ../main.c
Invoking: GCC C Compiler
gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"dome.d" -MT"dome.d" -o "dome.o" "../dome.c"
Invoking: GCC C Compiler
gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"main.d" -MT"main.d" -o "main.o" "../main.c"
Finished building: ../dome.c
Finished building: ../main.c
Building target: empty_linux
Invoking: GCC C Linker
gcc -o "empty_linux" ./dome.o ./main.o
Finished building target: empty_linux
Synchronized Attempt
make -j8 all --output-sync
yields (same result for -O/-Oline/etc):
make: unrecognized option '--output-sync
Question
what the heck am I doing wrong??
The --output-sync option is only available in GNU make 4.0. Also, in your case you should use:
--output-sync=target
or
-Otarget
But this won't work with version 3.82.
I want to compile a C file for stellaris board. (cortex m4)
But the compiler always throws the following errors:
Building file: ../main.c
Invoking: Cross GCC Compiler
arm-none-eabi-gcc -DPART_LM4F120H5QR -DARM_MATH_CM4 -DTARGET_IS_BLIZZARD_RA1 -I/home/erbal/src/stellaris -I/usr/lib/gcc/arm-none-eabi/4.5.1/include-fixed -I/usr/lib/gcc/arm-none-eabi/4.5.1/include -I/usr/lib/gcc/x86_64-unknown-linux-gnu/4.8.2/include -O0 -g3 -Wall -c -fmessage-length=0 -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -MMD -MP -MF"main.d" -MT"main.d" -o "main.o" "../main.c"
as: unrecognized option '-mcpu=cortex-m4'
subdir.mk:21: recipe for target 'main.o' failed
make: *** [main.o] Error 1
You need to install the arm-none-eabi-binutils package in addition to arm-none-eabi-gcc.
You can use the GCC -B option to specify the prefix of the tool chain binaries, so the cross-compiler is used instead of the native.
Need to put the arm-none-eabi-c++ or arm-none-eabi-gcc together with the whole gcc folder [e.g inside arm-none-eabi folder]. Because compiler will depend on others binutils component/files as well.
Let's say you have the tool chain specific to ARM EABI at /usr/local/arduino-packages-1.6.8, ensure that /usr/local/arduino-packages-1.6.8/arduino/tools/arm-none-eabi-gcc/4.8.3-2014q1/arm-none-eabi/bin is readable and in the PATH environment variable and its contents have executable permissions.