Is there any sample makefile project that only consists of .c and .h files?
I am using gcc, Windows 8.1
I found this, but it does not work:
#########################
# customise these
CFILES := sampleA.c main.c sampleB.
PROG := prog
CFLAGS := -Wall -Wextra -g
LDFLAGS :=
########################
# -MMD generates dependencies while compiling
CFLAGS += -MMD
CC := gcc
OBJFILES := $(CFILES:.c=.o)
DEPFILES := $(CFILES:.c=.d)
$(PROG) : $(OBJFILES)
$(LINK.o) $(LDFLAGS) -o $# $^
clean :
rm -f $(PROG) $(OBJFILES) $(DEPFILES)
-include $(DEPFILES)
I get the following error:
undefined reference to sendto#24,socket#12,inte_addre#4, htons#04,bind#12, select#20,recvfrom#24, WSAGetLastError#0,WSAStartup#8,ioctlsocket#12
You can refer the below Makefile
exe ?= prog
CC = gcc
CFLAGS = -g -Wall -Wextra -MMD
LDFLAGS =
all: $(exe)
$(exe) : sampleA.c sampleB.c main.c
$(CC) $(CFLAGS) $^ -o $#
clean:
-rm $(exe)
Here prog is output executable at the end of make.
You are missing some required library, wsock32 and ws2_32 if I'm not mistaken.
Use this Makefile:
EXE := prog.exe
SRC := $(wildcard *.c)
OBJ := $(SRC:.c=.o)
DEP := $(OBJ:.o=.d)
CC := gcc
CPPFLAGS := -MMD -MP
CFLAGS := -W -Wall -g
LDFLAGS :=
LDLIBS := -lwsock32 -lws2_32
.PHONY: all clean fclean re
all: $(EXE)
$(EXE): $(OBJ)
$(CC) $(LDFLAGS) $^ $(LDLIBS) -o $#
clean:
$(RM) $(OBJ) $(DEP)
fclean: clean
$(RM) $(EXE)
re: fclean all
-include $(DEP)
Related
I have to following folder structure in various projects :
myproject/
obj/
src/
file1.c
file2.c
file3.c
inc/
myproject.h
Makefile
I have the following Makefile :
NAME := myproject
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
HEADERS := $(INCDIR)/myproject.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
SRCS := file1.c file2.c file3.c
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(COMPILE.c) $< -o $#
all: $(NAME)
$(NAME): $(OBJECTS) $(HEADERS) Makefile
$(LINK.o) $< -o $#
clean:
$(RM) $(OBJECTS)
fclean: clean
$(RM) $(NAME)
re: fclean all
.PHONY: all clean fclean re
Here is what I am looking to achieve :
I would like to put all .o files under obj/.
The final executable should be at the root of the myproject/ folder.
If a .c file changes, only this file should be recompiled.
If the Makefile or the .h changes, I would like to recompile everything.
However, I when I run this Makefile I get make: *** No rule to make target obj/file1.o', needed by myproject'. Stop..
Could anyone help me fix this Makefile and give me advice on how to improve it?
EDIT
Here is a new version of the Makefile based on the comments.
NAME := myproject
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
HEADERS := $(INCDIR)/myproject.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
REMOVE := $(RM) $(RMFLAGS)
SRCS := file1.c file2.c file3.c
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(COMPILE.c) $< -o $#
all: $(NAME)
$(NAME): $(OBJECTS)
$(LINK.o) -o $(NAME) $^
clean:
$(REMOVE) $(OBJECTS)
fclean: clean
$(REMOVE) $(NAME)
re: fclean all
.PHONY: all clean fclean re
This version works, but I am still unsure how to trigger recompilation of the Makefile or the .h changes.
Thanks to #MadScientist and #HardcoreHenry I have managed to fix the Makefile. Here is the final version :
# Edit the $(NAME) and $(SRCS) variables as necessary.
NAME := myprogram
SRCS := file1.c file2.c file3.c
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
# Edit the $(HEADERS) variable as necessary.
HEADERS := $(INCDIR)/myprogram.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
REMOVE := $(RM) $(RMFLAGS)
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
#mkdir -p $(#D)
$(COMPILE.c) $< -o $#
all: $(NAME)
$(OBJECTS): $(HEADERS) Makefile
$(NAME): $(OBJECTS)
$(LINK.o) -o $(NAME) $^
clean:
$(REMOVE) $(OBJECTS)
fclean: clean
$(REMOVE) $(NAME)
re: fclean all
.PHONY: all clean fclean re
I am trying to compile my Makefile to make library from different directories. The library is successfully compiled but I am facing the following warning
/Applications/Xcode.app/Contents/Developer/usr/bin/make -C ./libft
make[1]: Nothing to be done for `all'.
gcc -Wall -Werror -Wextra -c srcs/ft*.c libft/ft*.c -I ./includes
ar rcs libftprintf.a srcs/ft*.c libft/ft*.c*****
warning: /Applications/Xcode.app/Contents/Developer/Toolchains/Xcod
eDefault.xctoolchain/usr/bin/ranlib: archive library: libftprintf.a
the table of contents is empty (no object file members in the libr
ary define global symbols)
Please kindly advise on how to solve this warning. The structure of my directory is as follow:
steh#u90z01s01 printf % ls
Makefile includes main.c libft srcs
My Makefile is as following
NAME := libftprintf.a
CC := gcc
AR := ar rcc
CFLAGS:= -Wall -Werror -Wextra -c
SRCS = srcs/ft*.c libft/ft*.c
INCLUDES = ./includes
OBJ_FILES = $(SRCS:%.c = %.o)
$(NAME): $(OBJ_FILES)#.fr
$(MAKE) -C ./libft
$(CC) $(CFLAGS) $(SRCS) -I $(INCLUDES)
$(AR) $(NAME) $(OBJ_FILES)
all: $(NAME)
clean:
#echo "Cleaning..."
rm -rf $(NAME) ft*.o
fclean:
rm -rf $(NAME)
re: fclean all
norm:
#norminette $(LIB_FILES)
.PHONY: clean fclean all re norm
This is my latest code
NAME := libftprintf.a
CC := gcc
AR := ar rcs
CFLAGS := -Wall -Werror -Wextra -c
SRCS = ./libft/ft*.c ./srcs/ft*.c
OBJS = ft*.o
LIBFT = ./libft
INC = ./includes
# Colors
GREEN= \033[1;32m
RED= \033[1;31m
all: $(NAME)
$(NAME):
#make re -C $(LIBFT)
#$(CC) $(CFLAGS) $(SRCS) -I $(INC)
#$(AR) $(NAME) $(OBJS)
#ranlib $(NAME)
#echo "$(GREEN)ft_printf compiled!"
CC= gcc
CFLAGS= -Wall -g
INCLUDES= -I/usr/local/include/
LFLAGS= -L/usr/local/lib64
LDFLAGS=
LIBS= -L. -lrabbitmq
SRCS= amqp_connection.c amqp_consumer.c amqp_deconnection.c amqp_producer.c amqp_utils.c
OBJS= $(SRCS:.c=.o)
EXEC=amqp_test
.PHONY: all
all: $(EXEC)
#echo "$(MAKE) : Tout est généré"
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS) $(LDFLAGS) $(INCLUDES) $(LFLAGS) $(LIBS)
.PHONY: clean
clean:
$(RM) *~ *.o $(EXEC)
I want to generate a library not an executable
Can you help me please ?
I launched "make" and the result is :
make: *** No rule to make target
amqp_connection.o', needed by amqp_test'. Stop. amqp_test is the
name of the file which contain the main().
The sources are :
amqp_connection / amqp_consumer /amqp_deconnection / amqp_producer
This is an example file using some common practices. Here, I'm redefining the source directory and the object directory, and defining an implicit rule to build the objects given a source in a different directory.
CC := gcc
CFLAGS := -Wall -g
SRCDIR := src
OBJDIR := obj
INCLUDES := -I/usr/local/include/
LFLAGS := -L/usr/local/lib64
LDFLAGS :=
LIBS := -L. -lrabbitmq
SRCS_RAW := amqp_connection.c amqp_consumer.c amqp_deconnection.c amqp_producer.c amqp_utils.c
SRCS := $(addprefix $(SRCDIR)/,$(SRCS_RAW))
OBJS := $(addprefix $(OBJDIR)/,$(SRCS_RAW:.c=.o))
EXEC := amqp_test
$(info DEBUG: SRCS=$(SRCS))
$(info DEBUG: OBJS=$(OBJS))
$(info DEBUG: EXEC=$(EXEC))
.PHONY: all
all: $(EXEC)
#echo "$(MAKE) : Tout est généré"
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS) $(LDFLAGS) $(INCLUDES) $(LFLAGS) $(LIBS)
#rule to create object directory if it doesnt exist
$(OBJDIR):
mkdir $(OBJDIR)
#define implicit rule to build objects in their own directory
#(note -- order only dependency on object directory)
$(OBJS): $(OBJDIR)/%.o: $(SRCDIR)/%.c | $(OBJDIR)
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
.PHONY: clean
clean:
$(RM) *~ $(EXEC)
$(RM) -r $(OBJDIR)
hi im trying to create a shared object for my native library to be accessed by my java project but when i run the makefile i get the error unable to link
here's my makefile
LIB_FILE = ../lib/libpktartintf.so
SRCS := $(wildcard *.c)
OBJS := $(SRCS:.c=.o)
DEPS := $(OBJS:.o=.d)
CC = gcc
INCFLAGS = -I../include
CFLAGS += $(INCFLAGS) -Wall -MMD -MP
LDFLAGS = -shared
$(LIB_FILE): $(OBJS)
$(CC) -c $(LDFLAGS) $(CFLAGS) -o $# $<
.PHONY: clean
clean:
rm -f *.o *.d $(LIB_FILE)
-include $(DEPS)
when I "make" it im getting the following error
gcc -c -shared -I../include -Wall -MMD -MP -o ../lib/libpktartintf.so pktartintf.o
gcc: warning: pktartintf.o: linker input file unused because linking not done
any idea why
So, I can understand what the problem is here, but I can't quite figure out how to fix it -- Because it is compiling files from a different directory, but throwing the .a library file and executable into the root...It seems that the makefile is expecting them to be in their source directory, and that's why it rebuilds every time even when no changes are made.
Problem is, my school is very strict on folder structure, so it needs to compile exactly how it is, I just need to figure out how to let the makefile know the executable and library file DO exist, in the root directory.
Here is my Makefile:
NAME = fillit
LIB = libft.a
CC = gcc
CFLAGS = -Wall -Wextra -Werror
RM = /bin/rm -rf
SRC = main.c validation.c create_piece.c game_board.c solver.c tables.c \
trimmer.c
LIBSRC = ft_putchar.c ft_putstr.c ft_strcpy.c ft_strnew.c ft_strdel.c \
ft_strequ.c ft_putendl.c ft_error.c
LIBLIST := $(shell ls -1 libft | grep .c$$)
LIBOBJ := $(LIBLIST:.c=.o)
LIBOBJ := $(addprefix libft/, $(LIBOBJ))
SRCLIST := $(shell ls -1 src | grep .c$$)
SRCOBJ := $(SRCLIST:.c=.o)
SRCOBJ := $(addprefix src/, $(SRCOBJ))
.PHONY: all $(NAME) lib
all: $(NAME)
libft/%.o: libft/%.c
$(CC) $(CFLAGS) -c -o $# $<
src/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
lib:
ar rc $(LIB) $(LIBOBJ)
ranlib $(LIB)
debug:
$(CC) $(CFLAGS) $(addprefix libft/, $(LIBLIST)) $(addprefix src/, $(SRCLIST)) -g -o fillit
$(NAME): $(LIBOBJ) $(SRCOBJ) lib
$(CC) $(CFLAGS) $(SRCOBJ) -L. -lft -o fillit
clean:
$(RM) $(SRCOBJ)
$(RM) $(LIBOBJ)
fclean: clean
$(RM) $(NAME)
$(RM) $(LIB)
re: fclean all
re-db: fclean debug
It's working fine for compiling the .o files, it only does that once, but if I continue to type make, it still compiles this part:
➜ fillit git:(master) ✗ make
ar rc libft.a libft/ft_memset.o libft/ft_putchar.o libft/ft_putendl.o libft/ft_putstr.o libft/ft_strcpy.o libft/ft_strdel.o libft/ft_strequ.o libft/ft_strnew.o
ranlib libft.a
gcc -Wall -Wextra -Werror src/create_piece.o src/game_board.o src/main.o src/solver.o src/tables.o src/trimmer.o src/validation.o -L. -lft -o fillit
Want to thank kaylum for pointing me in the right direction, I have figured out how to solve this problem. I changed lib to $(LIB) and removed $(NAME) and lib from the phony list. Working makefile:
NAME = fillit
LIB = libft.a
CC = gcc
CFLAGS = -Wall -Wextra -Werror
RM = /bin/rm -rf
SRC = main.c validation.c create_piece.c game_board.c solver.c tables.c \
trimmer.c
LIBSRC = ft_putchar.c ft_putstr.c ft_strcpy.c ft_strnew.c ft_strdel.c \
ft_strequ.c ft_putendl.c ft_error.c
LIBLIST := $(shell ls -1 libft | grep .c$$)
LIBOBJ := $(LIBLIST:.c=.o)
LIBOBJ := $(addprefix libft/, $(LIBOBJ))
SRCLIST := $(shell ls -1 src | grep .c$$)
SRCOBJ := $(SRCLIST:.c=.o)
SRCOBJ := $(addprefix src/, $(SRCOBJ))
.PHONY: all
all: $(NAME)
libft/%.o: libft/%.c
$(CC) $(CFLAGS) -c -o $# $<
src/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
$(LIB):
ar rc $(LIB) $(LIBOBJ)
ranlib $(LIB)
debug:
$(CC) $(CFLAGS) $(addprefix libft/, $(LIBLIST)) $(addprefix src/, $(SRCLIST)) -g -o fillit
$(NAME): $(LIBOBJ) $(SRCOBJ) $(LIB)
$(CC) $(CFLAGS) $(SRCOBJ) -L. -lft -o $(NAME)
clean:
$(RM) $(SRCOBJ)
$(RM) $(LIBOBJ)
fclean: clean
$(RM) $(NAME)
$(RM) $(LIB)
re: fclean all
re-db: fclean debug