How can i know that my architecture support interrupts? If it supports then how can we implement a interrupt on some gpio pin? In my case some other board is sending interrupt on a gpio pin. can I detect this interrupt in u-boot level and process it in handler? i am using arm architecture.
Short answer, interrupts are not really used in U-Boot.
Ref1 Normally you don't need interrupts in U-Boot. U-Boot is strictly
single-tasking by nature and design.
Ref2 All the peripherals are implemented in polled mode.
Ref3 U-boot is polling by design (simplicity).
More good info here Enabling Interrupts in U-boot for ARM cortex A-9
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I am working on an ARMv7 project, which has 2 cores.
According to ARM GICv2 spec. there are 16 PPIs for each core.
So my understanding is the PPI is local to each ARM core, and it should be signaled to and handled by the core.
According to ARM GICv2 spec, the PPI should have the same irq_num for all cores.
I could NOT figure out how is a PPI handled by each core.
Let me use localtimer as an example, each core has an local timer which can interrupt the connected core, in this case, how to install/register the software interrupt handler for that timer interrupt? Or there is a global interrupt handler for the interrupt targets to each core?
I found the answer to it.
As GICv2 spec. says, each PPI is private to each Core, and it is not impacted by ITARGETSRn register. Some GIC registers are banked, so each core has its own register to access.
As for the local timer example, each core should configure the same GIC registers to setup the timer interrupt, and the timer interrupt handler can be ran on each core when the PPI is triggered.
This is the local timer interrupt, which can be used as scheduling tick.
Can any one tell me what is the buffer depth of Arm cortex M7 processor.Where can i find?Since i am net to the processor development?i need to know what is the buffer depth of UART in Arm Cortex M7 processor.
Arm CORTEX micros do not have any uarts. Those ones are developed by the chip venfors, and every single vendor has its own design. UARTS do not have hardware buffers only FIFOs of the size 2 or 4 depending on the uart design and vendor.
Microcontroller vendors design the UART part, ARM is only designing cortex -m core, NVIC (nested vectored interrupt controller) and some buses. One mcu vendor can put 1 byte uart buffer while another one can design it with 10 bytes fifo. That totally depends on the design of the mcu.
I want to stream data, byte-by-byte, from RAM to a port (GPIO pins) on an ARM Cortex M3 (and possibly M4 in future).
Is there a way of controlling the rate, relative to the bus speed?
i.e. if I'm running the M3 at 100MHz, can I do DMA at 10MHz, for example?
Is there a way of controlling the rate, relative to the bus speed?
Use a timer to trigger the DMA transfer.
if I'm running the M3 at 100MHz, can I do DMA at 10MHz, for example?
Depends on the microcontrollers implementation of GPIO, DMA and timer. Those are usually not ARM provided peripherials - vendors implement them in different ways.
In ARM architecture I have read that there are 3 kinds of interrupt :
PPI - Per processor interrupts
SPI - Shared processor interrupts
SGI - Software generated interrupts
I want to know what are these, and how they are different from each other ?
Software Generated Interrupt (SGI)
This interrupt is generated explicitly by software by writing to a dedicated distributor register, the Software Generated Interrupt Register. It is most commonly used for inter-core communication. SGIs can be targeted at all, or at a selected group of cores in the system. Interrupt numbers 0-15 are reserved for this. The software manages the exact interrupt number used for communication.
Private Peripheral Interrupt (PPI)
This interrupt is generated by a peripheral that is private to an individual core. Interrupt numbers 16-31 are reserved for this. PPIs identify interrupt sources private to the core, and are independent of the same source on another core, for example, per-core timer.
Shared Peripheral Interrupt (SPI)
This interrupt is generated by a peripheral that the Interrupt Controller can route to more than one core. Interrupt numbers 32-1020 are used for this. SPIs are used to signal interrupts from various peripherals accessible across the whole system.
You can read here
I am using mini2440 arm board, and GPIO to control the hardware connected with the GPIO. I am using BSP that ships with the cd of the board. I have only enabled functionality which I will need for running the hardware.
I have disabled audio, Ethernet and unnecessary stuff in kernel, so that it don;t cause interrupt hence CPU attention. But the problem is sometimes some interrupt occur on the GPIO and hardware do malfunction. I know I can see all interrupt via cat /proc/interrupt, but how should i know which interrupt occur on GPIO from which device?
I am running my application with highest nice priority (-20), but still sometime external interrupt occur.
When i send data on GPIO, only TimerTick of s3c2440 do interrupt, but that's fine, it is require, but not other. Please tell me how to find which interrupt occur (I know I can check it via cat /proc/interrupt) and how to disable (Disable interrupt on ethernet via ifconfig eth0 down) interrupt from kernel? Need some expert solution, I have tried the solution getting help from people but need some expert solution.
Disabling devices in the kernel has no real efect on interrupts (generated by the hardware), it just affects how software handles them. If the device isn't present, no interrupts get generated. And Linux was written by absolute performance freaks, barring misbehaving hardware the interrupt handling is nearly as good/fast as it could be.
What exactly are you trying to do? Are you sure you aren't trying to get performance that your machine just can't deliver?