compiling C project with makefile - c

I have a directory called reliability:
ls reliability
analyze.c appl.sh constr.c creer.c greedys.c Makefile
Now I want to install and compile it:
First of all the content of Makefile is:
CC = gcc
CFLAGS = -g -Wall -pthread
SRCS = constr.c creer.c analyze.c greedys.c
PROG = constr creer analyze greedys
all: $(PROG)
constr: constr.c
$(CC) $(CFLAGS) -o constr constr.c
creer: creer.c
$(CC) $(CFLAGS) -o creer creer.c
analyze: analyze.c
$(CC) $(CFLAGS) -o analyze analyze.c
greedys: greedys.c
$(CC) $(CFLAGS) -o greedys greedys.c
clean:
rm -f $(PROG)
When I start compiling it:
make -f Makefile
The error occurs:
gcc -g -Wall -pthread -o constr constr.c
/tmp/cca4NKQl.o: In function `main':
/home/t1/Desktop/reliability/constr.c:89: undefined reference to `exp'
/home/t1/Desktop/reliability/constr.c:89: undefined reference to `exp'
/home/t1/Desktop/reliability/constr.c:89: undefined reference to `pow'
/home/t1/Desktop/reliability/constr.c:89: undefined reference to `log'
collect2: ld returned 1 exit status
make: *** [constr] Error 1
I pass these errors by adding -lm to gcc,
Even when I change CFLAGS from Makefile to CFLAGS = -g -Wall -pthread -lm there is also that error.
My question:
Should I compile all .c programs separately now?
Thank you I really need help,
UPDATE
When I compile creer.c there is an error:
creer.c:39:10: warning: unused variable ‘val2’ [-Wunused-variable] creer.c:38:7:
warning: unused variable ‘val’ [-Wunused-variable]
Part of creer.c is:
void values(){
int val;
double val2;
FILE *fp;
fp = fopen("instances","r");
fseek(fp,0,SEEK_SET);
if(fscanf(fp,"%d",&p)==EOF){printf("EOF\n");}
if(fscanf(fp,"%d",&m)==EOF){printf("EOF\n");}
if(fscanf(fp,"%d",&K)==EOF){printf("EOF\n");}
if(fscanf(fp,"%lf",&lambda_com)==EOF){printf("EOF\n");}
if(fscanf(fp,"%d",&num_inst)==EOF){printf("EOF\n");}
if(fscanf(fp,"%d",&boundl)==EOF){printf("EOF\n");}
if(fscanf(fp,"%d",&boundp)==EOF){printf("EOF\n");}
fclose(fp);
}

You need to add that linker option -lm to the end of your command line.
Do something like this:
LDFLAGS=-lm
...
constr: constr.c
$(CC) $(CFLAGS) -o constr constr.c $(LDFLAGS)
Or you could define a pattern rule:
%: %.c
$(CC) $(CFLAGS) -o $# $< $(LDFLAGS)
and use it to replace all those rules for constr, creer, and so on.

Related

Makefile adding libraries from others directory

I want to create a Makefile for a big C project, with files divided into directories. What I wrote is
CC = gcc
AR = ar
ARFLAGS = rvs
CFLAGS += -std=c99 -Wall -g
INCDIR = ./include
LIBDIR = ./lib
SRCDIR = ./src
BINDIR = ./bin
OBJDIR = ./obj
TESTDIR = ./testfile
INCLUDES = -I.
LDFLAGS = -L/lib
LIBFUNCTIONS = /-lfunctions
LIBTH = -lpthread
LIBUTILITY = /-lutility
OPTFLAGS = -O3 -DNDEBUG
TARGETS = $(BINDIR)/test_functions \
.PHONY: all clean cleanall test1 test2
.SUFFIXES: .c .h
$(BINDIR)/%: $(SRCDIR)/%.c
$(CC) $(CFLAGS) $(INCLUDES) $(OPTFLAGS) -o $# $<
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(CC) $(CFLAGS) $(INCLUDES) $(OPTFLAGS) -c -o $# $<
all : $(TARGETS)
$(BINDIR)/test_functions: $(OBJDIR)/test_functions.o $(LIBDIR)/libutility.a $(LIBDIR)/libfunctions.a
$(CC) $(CFLAGS) $(INCLUDES) $(FLAGS) $(LDFLAGS) -o $# $< $(LIBUTILITY) $(LIBFUNCTIONS)
$(OBJDIR)/test_functions.o: $(SRCDIR)/test_functions.c $(INCDIR)/utility.h $(LIBDIR)/libutility.a $(INCDIR)/functions.h $(LIBDIR)/libfunctions.a
$(CC) $(CCFLAGS) $(INCLUDES) $(FLAGS) -c -o $# $<
$(LIBDIR)/libutility.a: $(OBJDIR)/utility.o $(INCDIR)/utility.h
$(AR) $(ARFLAGS) $# $<
$(LIBDIR)/libfunctions.a: $(OBJDIR)/functions.o $(INCDIR)/functions.h $(INCDIR)/utility.h
$(AR) $(ARFLAGS) $# $<
clean :
rm -f $(TARGETS)
cleanall : clean
\rm -f *.o *~
the problem is that when I try to compile the project using the makefile, the result is
gcc -std=c99 -Wall -g -I. -L/lib -o bin/test_functions obj/test_functions.o -lutility -lfunctions
/usr/bin/ld: impossibile trovare -lutility
/usr/bin/ld: impossibile trovare -lfunctions
collect2: error: ld returned 1 exit status
make: *** [Makefile:54: bin/test_functions] Error 1
it seems that the compiler cannot find the libraries. what can I do to make it work properly?
You have this:
LIBDIR = ./lib
then in your link line you have this:
LDFLAGS = -L/lib
Notice the difference?
Why don't you just say:
LDFLAGS = -L$(LIBDIR)
to avoid repeating yourself (and getting it wrong)?

/usr/bin/ld: cannot find -lioutil in Makefile

I want to do makefile as the following, but I received this error:
gcc frparse.o frtags.o frscan.o frinit.o frstop.o frfoot.o frio.o -L/usr/local/image/lib/sgi -lioutil -lutil -o frparse
/usr/bin/ld: cannot find -lioutil
collect2: error: ld returned 1 exit status
Makefile:17: recipe for target 'frparse' failed
make: *** [frparse] Error 1
I would appreciate it if you guide me.
IMLIB = /usr/local/image/lib/sgi
LLIBS = -lioutil -lutil
it: frparse frcheck pgrep
OBJ = frparse.o frtags.o frscan.o frinit.o frstop.o frfoot.o frio.o
frparse.o: Makefile frparse.h frio.h frproto.h frstop.h frparse.c
frinit.o: Makefile frparse.h frproto.h frinit.c
frscan.o: Makefile frio.h frstop.h frscan.c
frfoot.o: Makefile frparse.h frproto.h frstop.h frfoot.c
frtags.o: Makefile frparse.h frio.h frproto.h frstop.h frtags.c
frstop.o: Makefile frstop.h frstop.c
frio.o: Makefile frio.c
frparse: $(OBJ)
gcc $(OBJ) -L$(IMLIB) $(LLIBS) -o $#
frcheck: frcheck.o
gcc frcheck.o -L$(IMLIB) $(LLIBS) -o $#
pgrep: pgrep.o
gcc pgrep.o -L$(IMLIB) $(LLIBS) -o $#
.c.o:
# cc -c -O2 -mips2 $<
gcc -c -g $<
regarding:
.c.o:
# cc -c -O2 -mips2 $<
gcc -c -g $<
The comment # must ALSO be indented via a <tab> otherwise the recipe never performs the third line
Also, the syntax is a bit obsolete suggest:
%.o:%.c
for the first line of the recipe
However, regarding your question:
Is there actually a library file named libioutil.so in the directory:
/usr/local/image/lib/sgi

Trying to use matlab's libmat.dll, but the compiler doesn't recognize the function from the library

I am trying to use matlab libmat.dll in a C application. To compile my C application I use MinGW, for now I use matlab exemple "matcreate.c" and try to compile it, so the projects consist of only one file : main.c .
Here is the makefile I use :
MATINCLUDE = "C:\Program Files\MATLAB\R2010a\extern\include"
MATLIBRARY = "C:\Program Files\MATLAB\R2010a\bin\win64"
#
CC = gcc
LD = gcc
CFLAGS = -O3 -Wall
LFLAGS = -Wall -O3
LIBS = -I$(MATINCLUDE) -L$(MATLIBRARY)
#
PROG = matTest
LISTEOBJ = \
main.o
.c.o :
$(CC) -c $(CFLAGS) $(LIBS) -o $# $<
all : $(PROG)
$(PROG) : $(LISTEOBJ)
$(LD) -o $(PROG) $(LFLAGS) $(LISTEOBJ) $(LIBS)
clean :
rm -f *.obj
Here is what I get in the console
E:\Users\Desk\Dropbox\matTest>make
gcc -c -O3 -Wall -I"C:\Program Files\MATLAB\R2010a\extern\include" -L"C:\Pr
ogram Files\MATLAB\R2010a\bin\win64" -o main.o main.c
gcc -o Hello_world -Wall -O3 main.o -I"C:\Program Files\MATLAB\R2010a\extern\i
nclude" -L"C:\Program Files\MATLAB\R2010a\bin\win64"
main.o:main.c:(.text.startup+0x48): undefined reference to `matOpen'
main.o:main.c:(.text.startup+0x6e): undefined reference to `mxCreateDoubleMatrix
_730'
e:/mingw/bin/../lib/gcc/mingw32/4.8.1/../../../../mingw32/bin/ld.exe: main.o: ba
d reloc address 0x6e in section `.text.startup'
e:/mingw/bin/../lib/gcc/mingw32/4.8.1/../../../../mingw32/bin/ld.exe: final link
failed: Invalid operation
collect2.exe: error: ld returned 1 exit status
make: *** [Hello_world] Error 1
Why do I have "undefined reference to matOpen'" and "undefined reference to mxCreateDoubleMatrix" ?? those function are declared in mat.h. and I added #include "mat.h" to the begining of main.c
thank you
Looks like you have included the path to the matlab library, but not the library itself. You need to add a -l<libraryname> to your link line.

Any Missing code in my Make file

i wrote a makefile with some commands.after running command make got a errors undefined reference to sqrtand undefined reference to exp
my make file :
CFILES = smLe.c iniTra.c le.c res.c uti.c smClass.c ini.c clas.c
OBJECTS = smLe.o iniTra.o le.o res.o uti.o smClass.o ini.o clas.o
OBJECTS1 = smLe.o iniTra.o le.o res.o uti.o
OBJECTS2 = smClass.o ini.o clas.o
CFLAGS = -O -lm
CC = gcc
.c .o:
$(CC) $(CFLAGS) $(OBJECTS) -c $<
p1: $(OBJECTS1)
$(CC) $(CFLAGS) $(OBJECTS1) -o $#
p2: $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS2) -o $#
smLe.o: iniTra.h le.h res.h
iniTra.o: iniTra.h
le.o: iniTra.h uti.h le.h
res.o: iniTra.h le.h res.h
smClass.o: ini.h clas.h
ini.o: ini.h clas.h
clas.o: ini.h clas.h
Is it any thing missing in my make file.why this error occur in this make file code?please help me ..thanks
-lm is an LDLIB, you pass it to the linker
CFLAGS = -O
LDLIBS = -lm
CC = gcc
.c .o:
$(CC) $(CFLAGS) $(OBJECTS) -c $<
p1: $(OBJECTS1)
$(CC) $(OBJECTS1) -o $# $(LDLIBS)
Libraries have to appear after object files that call what is in them on the command line.

Makefile - wrong sequence of compiling

In makefile below I'm trying to compile one directory, but make against my will is trying to do it in wrong order. It's starting from compiling main.o and later it goes straight to compiling console. I have no idea why it's not trying to solve all dependences before it. I just get:
user#ubuntu:~/Dokumenty/Sysopy/cw1/zad3b$ make
gcc -c -Wall -I ./src/include src/main.c
gcc -o macierze main.o
main.o: In function `main':
main.c:(.text+0x28): undefined reference to `wczytaj'
main.c:(.text+0x31): undefined reference to `wczytaj'
main.c:(.text+0x7e): undefined reference to `suma'
...
collect2: ld returned 1 exit status make: *** [console] Błąd 1
Here's a makefile:
############ makra #############
CC = gcc
CFLAGS = -Wall -I ./src/include
LFLAGS =
VPATH = ./src/operacje: ./src/we_wy: ./src/reszta
########### pliki ##############
SRC_CONSOLE = wczytaj_konsola.c wypisz_konsola.c
SRC_FILE = wczytaj_plik.c wypisz_plik.c pliki.c
SRC_FUNCTION = suma.c roznica.c iloczyn.c macierz.c
HEADERS = suma.h roznica.h iloczyn.h wypisz.h wczytaj.h macierz.h
OBJ_SONSOLE = $(SRC_CONSOLE:.c=.o)
OBJ_FILE = $(SRC_FILE:.c=.o)
OBJ_FUNCTION = $(SRC_FUNCTIONS:.c=.o)
console: $(OBJ_CONSOLE) $(OBJ_FUNCTION) main.o
$(CC) $(LFLAGS) -o macierze $^
file: $(OBJ_FILE) $(OBJ_FUNCTION) main.o
$(CC) $(LFLAGS) -o macierze $^
console_logs: $(OBJ_CONSOLE) $(OBJ_FUNCTION) main.o
$(CC) $(LFLAGS) -o macierze $^
file_logs: $(OBJ_FILE) $(OBJ_FUNCTION) main.o
$(CC) $(LFLAGS) -o macierze $^
############# objekty ##############
main.o:
$(CC) -c $(CFLAGS) src/main.c
$(OBJ_CONSOLE): $(SRC_CONSOLE)
$(CC) -c $(CFLAGS) $^
$(OBJ_FILE): $(SRC_FILE)
$(CC) -c $(CFLAGS) $^
$(OBJ_FUNCTION): $(SRC_FUNCTION)
$(CC) -c $(CFLAGS) $^
%logs : LFLAGS += -D KOMUNIKATY
file% : LFLAGS += -D PLIKI
./PHONY: clean
clean:
rm -f *.o
rm -f ./src/include/*.gch
rm -f macierze
you write : OBJ_FUNCTION = $(SRC_FUNCTIONS:.c=.o)
instead of : OBJ_FUNCTION = $(SRC_FUNCTION:.c=.o)
and
OBJ_SONSOLE = $(SRC_CONSOLE:.c=.o)
instead of OBJ_CONSOLE = $(SRC_CONSOLE:.c=.o)

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