I'm trying to compile a project that includes various files from X11 in my /usr/include directory. It compiles fine on a remote linux machine, but when I attempt to run the make file I get the following error:
$ make clean; make
rm -f xrobot.o mobile_base.o arm.o eye.o object.o 4D_math.o Xkw/Canvas.o Xkw/Sli
der.o Xkw/Xkw.o lib/simulator.a *~
cd ./Xkw; make; cd ..; \
make[1]: Entering directory `C:/cygwin/home/Gene/roger/mmRogerSpring2014/RogerSi
mulator/Xkw'
gcc -c -g -I. -I/usr/include/X11 -I/usr/X11R6/include Canvas.c
Canvas.c:9:22: fatal error: X11/Xos.h: No such file or directory
compilation terminated.
make[1]: *** [Canvas.o] Error 1
make[1]: Leaving directory `C:/cygwin/home/Gene/roger/mmRogerSpring2014/RogerSim
ulator/Xkw'
gcc -c -g -I. -I/usr/X11R6/include -I/usr/include/X11 -I./include xrobot.c
In file included from xrobot.c:11:0:
Xkw/Xkw.h:12:27: fatal error: X11/Intrinsic.h: No such file or directory
compilation terminated.
make: *** [xrobot.o] Error 1
However, I know for a fact that the files are there, I can do
$ cat /usr/include/X11/Xos.h
And read the file.
Here is my make file:
# replace this with the top of your X11 tree
# X11 = /exp/rcf/share/X11R5
X11 = /usr/X11R6
############## do not change below this line ####################
ROGERINCDIR = ./include
XINCDIR = $(X11)/include
XLIBDIR = $(X11)/lib
EDLAB_XINCDIR = /usr/include/X11
XAWLIB = -lXaw
XMULIB = -lXmu
XTOOLLIB = -lXt
XLIB = -lX11
XEXTLIB = -lXext
MATHLIB = -lm
LIBS = -L$(XLIBDIR) $(XAWLIB) $(XMULIB) $(XTOOLLIB) $(XLIB) $(XEXTLIB) \
$(MATHLIB)
RM = rm -f
CC = gcc
#CCFLAGS = -c -O $(OPT) -I. -I$(XINCDIR)
CCFLAGS = -c -g -I. -I$(XINCDIR) -I$(EDLAB_XINCDIR) -I$(ROGERINCDIR)
.SUFFIXES: .c .o
.c.o:
$(CC) $(CCFLAGS) $<
############## do not change above this line ####################
ROGERLIB = lib/simulator.a
OFILES1 = xrobot.o \
mobile_base.o \
arm.o \
eye.o \
object.o \
4D_math.o
XKWOFILES = Xkw/Canvas.o Xkw/Slider.o Xkw/Xkw.o
#XKWOFILES = Xkw/Canvas.o Xkw/Xkw.o
HFILES = Roger.h simulate.h control.h modes.h
all: subdirs $(OFILES1) $(ROGERLIB)
subdirs:
cd ./Xkw; make; cd ..; \
#$(ROGERLIB): $(OFILES1)
# $(CC) -o $# $(OFILES1) $(XKWOFILES) $(LIBS)
$(ROGERLIB): $(OFILES1) $(XKWOFILES)
ar r $(ROGERLIB) $(OFILES1) $(XKWOFILES)
clean:
$(RM) $(OFILES1) $(XKWOFILES) $(ROGERLIB) *~
#mobile_base.o: Roger.h simulate.h control.h
#arm.o: Roger.h simulate.h control.h
#eye.o: Roger.h simulate.h control.h
#object.o: Roger.h simulate.h control.h
#xrobot.o: Xkw/Xkw.h Roger.h simulate.h control.h
#tele_interface.o: Roger.h simulate.h control.h modes.h
Edit: I've changed the X11 variable at the top of the make file to be /usr/include instead of /usr/X11R6. It made no difference.
Edit 2: Here's the error with the above mentioned alternative include path.
$ make clean; make
rm -f xrobot.o mobile_base.o arm.o eye.o object.o 4D_math.o Xkw/Canvas.o Xkw/Sli
der.o Xkw/Xkw.o lib/simulator.a *~
cd ./Xkw; make; cd ..; \
make[1]: Entering directory `C:/cygwin/home/Gene/roger/mmRogerSpring2014/RogerSi
mulator/Xkw'
gcc -c -g -I. -I/usr/include/X11 -I/usr/X11R6/include Canvas.c
Canvas.c:9:22: fatal error: X11/Xos.h: No such file or directory
compilation terminated.
make[1]: *** [Canvas.o] Error 1
make[1]: Leaving directory `C:/cygwin/home/Gene/roger/mmRogerSpring2014/RogerSim
ulator/Xkw'
gcc -c -g -I. -I/usr/include/include -I/usr/include/X11 -I./include xrobot.c
In file included from xrobot.c:11:0:
Xkw/Xkw.h:12:27: fatal error: X11/Intrinsic.h: No such file or directory
compilation terminated.
make: *** [xrobot.o] Error 1
You should include X11/Xos.h as:
#include <X11/Xos.h>
If you include it as:
#include "X11/Xos.h"
it will be searched for relative to the source file, not in the -I directories.
That may be the issue.
Related
I´m trying to create a Makefile that build a lib and compile the file. My problem is that depending on the %.c file I need to compile with different lib.
The SRC_MLX need the $(LFLAGS) and the SRC don´t. So the gcc compiler don´t allow me to compile the SRC with the LFLAGS. That´s the reason I need to separate.
I´ve tried this way:
SRCS = $(DIR_SRC)/ft_utils.c \
$(DIR_SRC)/ft_adt.c \
$(DIR_SRC)/ft_circle.c \
$(DIR_SRC)/ft_line.c \
$(DIR_SRC)/ft_trgb.c \
$(DIR_SRC)/ft_quadrilateral.c \
$(DIR_SRC)/ft_player.c \
$(DIR_SRC)/ft_color.c
SRCS_MLX = $(DIR_SRC)/win_update.c \
$(DIR_SRC)/ft_vars.c \
$(DIR_SRC)/ft_image.c \
$(DIR_SRC)/ft_map.c
$(NAME): $(LIB_NAME)
$(CC) $(CFLAGS) main.c -I. -I$(DIR_MLX) -L$(DIR_MLX) -L. $(LFLAGS) $(LIB_FLAG) -o $# -g
$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c
mkdir -p $(DIR_OBJ)
$(CC) $(CFLAGS) -c $< -I. -I$(DIR_MLX) -o $#
$(DIR_OBJ)/$(OBJ_MLX).o: $(DIR_SRC)/$(SRCS_MLX).c
mkdir -p $(DIR_OBJ)
$(CC) $(CFLAGS) -c $< -I. -I$(DIR_MLX) -L$(DIR_MLX) $(LFLAGS) -o $#
$(LIB_NAME): $(OBJ_MLX) LIB_OBJ
$(AR) $(LIB_NAME) $(OBJ)
ranlib $(LIB_NAME)
LIB_OBJ: $(OBJ)
$(AR) $(LIB_NAME) $(OBJ)
In the example above I´ve tried to create a lib with one kind of files and after that create a lib with the first lib with the others files. But I keep getting this error:
Makefile:41: warning: overriding recipe for target '.objs/'
Makefile:37: warning: ignoring old recipe for target '.objs/'
make: Warning: File 'Makefile' has modification time 454 s in the future
rm -f .objs/ft_utils.o .objs/ft_adt.o .objs/ft_circle.o .objs/ft_line.o .objs/ft_trgb.o .objs/ft_quadrilateral.o .objs/ft_player.o .objs/ft_color.o
rm -f libcub3d.a
rm -f main
make: *** No rule to make target 'src/src/win_update.c', needed by '.objs/win_update.o'. Stop.
How can I compile this objects with different lib?
P.S. Those are my variables:
DIR_OBJ = .objs
DIR_SRC = src
DIR_LIB = lib
DIR_MLX = ./minilibx-linux
NAME = main
LIB_NAME = libcub3d.a
OBJ = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS))
OBJ_MLX = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS_MLX))
CC = clang
CFLAGS = -Wall -Werror -Wextra
LFLAGS = -lmlx -lm -lX11 -lXext -lbsd
LIB_FLAG = -lcub3d
AR = ar -rc
RM = rm -f
These lines are definitely not right:
$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c
...
$(DIR_OBJ)/$(OBJ_MLX).o: $(DIR_SRC)/$(SRCS_MLX).c
along with the way you've defined SRCS and SRCS_MLX and these:
OBJ = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS))
OBJ_MLX = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS_MLX))
Just expand the variables in the rule in your head, or else ask make to expand it for you with the info function, and you'll see it's definitely not right:
$(info output is '$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c')
C_SOURCES = $(wildcard src/kernel/*.c)
C_HEADERS = $(wildcard src/kernel/*.h)
C_SRC_NOT_DIR = $(notdir $(C_SOURCES))
C_OBJS = $(C_SRC_NOT_DIR:%.c=%.o)
OBJS = $(C_OBJS:%=$(OBJS_DIR)%)
BOOT_DIR = src/boot/
KERNEL_DIR = src/kernel/
OBJS_DIR = objs/
BIN_DIR = bin/
temp.o: $(OBJS)
ld -m elf_i386 -o $# -Ttext 0x1000 $^ --oformat binary
$(OBJS_DIR)%.o : $(C_SOURCES)%.c $(C_HEADERS)
gcc -m32 -fno-pie -ffreestanding -c $< -o $#
clean:
rm -rf $(OBJS_DIR)*.o $(BIN_DIR)*.bin
This is my makefile. When I build I get:
make: *** No rule to build target "objs/k_print.o "required for" temp.o". Stop.
I suppose the problem is related to the pattern rule. Help?
The line
$(OBJS_DIR)%.o : $(C_SOURCES)%.c $(C_HEADERS)
is not right. C_SOURCES is set to be the list of .c files. Perhaps you meant to use:
$(OBJS_DIR)%.o : $(KERNEL_DIR)%.c $(C_HEADERS)
I am trying to create a makefile in C but i am facing some issues.
I have my main .c, one .c which keeps the functions implementations and one .h which keeps the functions declarations.
When i try to run the makefile, i get a fatal error.
here is my makefile:
INCL = prog.h
SRC = prog.c prog_fun.c
OBJ = $(SRC:.c=.o)
EXE = prog
CC = gcc
CFLAGS = -c
RM = rm -rf
all: prog
prog: prog.o prog_fun.o
gcc -o prog prog.o prog_fun.o
prog.o: prog.c
gcc -c prog.c
prog_fun.o: prog_fun.c prog.h
gcc -c prog.c
clean:
$(RM) $(OBJ) $(EXE)
The error i get is this:
gcc -c prog.c
prog.c:11:19: fatal error: prog.h: No such file or directory
compilation terminated.
Makefile:17: recipe for target 'prog.o' failed
make: *** [prog.o] Error 1
Can anyone please help me with this?
What you are trying to do by using this
prog_fun.o: prog_fun.c header.h
It should be only
prog_fun.o: prog_fun.c
Modify your make file as
xyz#xyz-PC:~$ vi makefile
INCL = header.h
SRC = prog.c prog_fun.c
OBJ = $(SRC:.c=.o)
EXE = prog
CC = gcc
CFLAGS = -c
RM = rm -rf
all: prog
prog: prog.o prog_fun.o
gcc -o prog prog.o prog_fun.o
prog.o: prog.c
gcc -c prog.c header.h
prog_fun.o: prog_fun.c
gcc -c prog_fun.c header.h
clean:
$(RM) $(OBJ) $(EXE)
next run it
xxyz#xyz-PC:~$ make
gcc -c prog.c header.h
gcc -c prog_fun.c header.h
gcc -o prog prog.o prog_fun.o
I hope it will work now and make sure indention is correct(not manual spaces, it should be tab key)
I am currently failing to write a good makefile and don't know the reason why.. -.-
This is my main.c:
#include <windows.h>
#include <stdio.h>
int main(int argc, char *argv[])
{
printf("MEEEEEP");
return (0);
}
This is my makefile:
# make SYSTEM= OS= ENVIRONMENT=
# Binaries to use
ifeq ($(ENVIRONMENT),MINGW)
CXX = i686-pc-mingw32-g++
else
CXX = g++
endif
REMOVE = rm -vf
RC = windres
EXE = .exe
#############################################################
# Info
ifeq ($(CXX),g++)
INFO_CXX = g++ -dumpversion; g++ -dumpmachine
endif
#############################################################
# Flags
DEBUG = -DDEBUG -g
OPTIMIZATION = -O2 #-Winline -finline-functions
CFLAGS = -Wall -Wextra -W -static $(DEBUG) $(OPTIMIZATION) -D$(SYSTEM) -D$(OS) -D$(ENVIRONMENT) $(PRGFLAGS)
ifeq ($(SYSTEM),I686)
CFLAGS += -m32
ifeq ($(OS),WIN32)
CFLAGS += -D_WIN32
endif
ifeq ($(ENVIRONMENT),MINGW)
CFLAGS += -fexceptions
endif
endif
LFLAGS =
#############################################################
# Files
CFILES = main.c
OBJS = ${CFILES:.c=.o}
#############################################################
# Include
INCLUDES = -I.
#############################################################
# Library
LIBRARIES =
#############################################################
# Targets
.PHONY: all
all:
#echo == Standard build: make SYSTEM=I686 OS=WIN32 ENVIRONMENT=MINGW
#echo
#echo
make SYSTEM=I686 OS=WIN32 ENVIRONMENT=MINGW gyro
#############################################################
# Implicit rules and filename extensions...
.SUFFIXES: .h .o .c
.c.o: %.h
#echo Compiling $< for $(SYSTEM) $(OS) $(ENVIRONMENT) ...
#echo MEEP
$(CXX) $(CFLAGS) $(INCLUDES) -c $< -o $#
#echo MEEP2
#############################################################
# Target rules
gyro: $(OBJS)
#echo Building software for $(SYSTEM) ...
#echo
$(CXX) $(CFLAGS) $(LFLAGS) -o $#$(EXE) $(OBJS) $(LIBRARIES)
#############################################################
# Clean
.PHONY: clean
clean:
$(REMOVE) $(OBJS)
#############################################################
# Info
.PHONY: info
info:
#echo
#echo Information about C++ Compiler/Linker:
#echo
$(INFO_CXX)
When i type in make gyro,
i receive the output:
Compiling main.c for Windows_NT ...
MEEP
g++ -Wall -Wextra -W -static -DDEBUG -g -O2 -D -DWindows_NT -D -I. -c main.c -o main.o
makeNew.mak:83: recipe for target `main.o' failed
make: *** [main.o] Error 1
But Line number 83 is behind .c.o: %.h. And i don’t understand why.
Does anyone have a solution for me?
You see the two empty -D entries in the g++ command line? They're causing the problem. You must have values in the -D items e.g. -DWIN32
if you're insistent on using something like -D$(SYSTEM) -D$(ENVIRONMENT) then you can use something like:
SYSTEM ?= generic
ENVIRONMENT ?= generic
in the makefile which gives them default values.
Your output looks to be missing the all important output:
<command-line>:0:1: error: macro names must be identifiers
<command-line>:0:1: error: macro names must be identifiers
just to clarify, what actually got sent to g++ was -D -DWindows_NT, i.e. define a preprocessor macro called -DWindows_NT; which is of course not a valid identifier (similarly for -D -I.)
I have 4 .c files hello.c,here.c,bye.c and main.c.
One header file mylib.h
The contents are as follows
hello.c
#include<stdio.h>
void hello()
{
printf("Hello!\n");
}
here.c
#include<stdio.h>
void here()
{
printf("I am here \n");
}
bye.c
#include<stdio.h>
void bye()
{
printf("Bye,Bye");
}
main.c
#include<stdio.h>
#include "mylib.h"
int main()
{
hello();
here();
bye();
return 1;
}
mylib.h
#ifndef _mylib_
#define _mylib_
void hello();
void here();
void bye();
#endif
The makefile for creating a static lib is :
Makefile
#Which Compiler
CC = gcc
#Compiler Flags
CFLAGS = - Wall -c -fPIC
DYNLINKFLAGS = -shared -W1,-soname,$#.0
PROG = main
PROG_OBJS = main.c
LIB = mylib
LIB_FILES = libmylib.so
LIB_MINOR = $(LIB_FILES).0.1
LIB_RELEASE = $(LIB_MINOR).0
LIB_OBJS = hello.o here.o bye.o
PATH = /home/srinivasa/cspp51081/labs/srinivasa.lab2.1
all: $(LIB_FILES) $(PROG)
#Create Lib with this file
$(LIB_FILES): $(LIB_OBJS)
$(CC) $(DYNLINKFLAGS) $^
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
#Compiling main program and link with shared library
$(PROG): $(PROG_OBJS)
$(CC) -o $(PROG) $(PORG_OBJS) -l$(LIB) -L$(PATH)
main.o: main.c
hello.o: hello.c
here.o: here.c
bye.o: bye.c
#clean files
clean:
rm -rf $(LIB_OBJS) $(LIB_FILES) $(LIB_RELEASE) $(LIB_MINOR) libmylib.so.0
Problem: When I execute the command
make -f Makefile all
I get the error:
gcc -Wall -fPIC -c -o hello.o hello.c
make: gcc: Command not found
make: * [hello.o] Error 127
Questions : How do I resolve this?
+++++
OK. Lets revert to your original code, but with a small difference.
Change DYNLINKFLAGS back to:
DYNLINKFLAGS = -shared -Wl,-soname,$#.0
Then change the library link to:
$(CC) $(DYNLINKFLAGS) -o $(LIB_RELEASE) $^
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
Do "rm -f lib*", build and then post make output.
There are a few bugs (just typos) I can see is:
space between - and Wall:
CFLAGS = - Wall -c -fPIC
^
PORG_OBJS should be PROG_OBJS
$(CC) -o $(PROG) $(PORG_OBJS) -L$(PATH)
^^^^
You are doing an absolute assignment to PATH. Now every executable called in makefile will be search in that directory. Since gcc is not found in that directory you get this error. To fix this you can either use a different variable name or add your directory to current path as:
PATH := $(PATH):/home/srinivasa/cspp51081/labs/srinivasa.lab2.1
^ ^^^^^^^^
Try changing this line from:
$(CC) -o $(PROG) $(PORG_OBJS) -l$(LIB) -L$(LIBPATH)
to:
$(CC) -o $(PROG) $(PORG_OBJS) -L$(LIBPATH) -l$(LIB)
The -L flag needs to precede the -l flags.
OK. First change:
DYNLINKFLAGS = -shared -W1,-soname,$#.0
to
DYNLINKFLAGS = -shared -W1,-soname,$#
Then change:
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
To:
ln -sf $# $(LIB_RELEASE)
ln -sf $# $(LIB_MINOR)
ln -sf $# $#.0
Then post the library links and the final executable link.