C_SOURCES = $(wildcard src/kernel/*.c)
C_HEADERS = $(wildcard src/kernel/*.h)
C_SRC_NOT_DIR = $(notdir $(C_SOURCES))
C_OBJS = $(C_SRC_NOT_DIR:%.c=%.o)
OBJS = $(C_OBJS:%=$(OBJS_DIR)%)
BOOT_DIR = src/boot/
KERNEL_DIR = src/kernel/
OBJS_DIR = objs/
BIN_DIR = bin/
temp.o: $(OBJS)
ld -m elf_i386 -o $# -Ttext 0x1000 $^ --oformat binary
$(OBJS_DIR)%.o : $(C_SOURCES)%.c $(C_HEADERS)
gcc -m32 -fno-pie -ffreestanding -c $< -o $#
clean:
rm -rf $(OBJS_DIR)*.o $(BIN_DIR)*.bin
This is my makefile. When I build I get:
make: *** No rule to build target "objs/k_print.o "required for" temp.o". Stop.
I suppose the problem is related to the pattern rule. Help?
The line
$(OBJS_DIR)%.o : $(C_SOURCES)%.c $(C_HEADERS)
is not right. C_SOURCES is set to be the list of .c files. Perhaps you meant to use:
$(OBJS_DIR)%.o : $(KERNEL_DIR)%.c $(C_HEADERS)
Related
This simple program (two .c files and one .h) compiles and links properly from the command line. However, my Makefile is throwing an error during the linking stage. Proper tab usage is in effect.
CC = gcc
BINDIR = bin/
OBJDIR = obj/
SRCDIR = src/
MKDIR = mkdir -p
RM = rm -rf
SRC = $(wildcard $(SRCDIR)*.c)
_OBJS = $(patsubst $(SRCDIR)%.c, %.o, $(SRC))
OBJS = $(addprefix $(OBJDIR), $(_OBJS))
CFLAGS = -Wall -g -Iinclude
.PHONY: all
all: $(BIN)
_BIN = a.out
BIN = $(addprefix $(BINDIR), $(_BIN))
$(BIN): $(OBJS) $(BINDIR)
$(CC) -o $# $(CFLAGS) $<
$(BINDIR):
$(MKDIR) $(BINDIR)
$(OBJS): $(SRC) $(OBJDIR)
$(CC) $(CFLAGS) -c $< -o $#
$(OBJDIR):
$(MKDIR) $(OBJDIR)
.PHONY: clean
clean:
#echo "Cleaning things up..."
$(RM) $(OBJDIR) $(BINDIR)
The program's files:
main.c
#include <stdio.h>
#include <stdlib.h>
#include "hellomake.h"
int main(void) {
myPrintHelloMake();
return EXIT_SUCCESS;
}
hellomake.c
#include <stdio.h>
#include "hellomake.h"
void myPrintHelloMake(void) {
puts("Hello makefiles!");
}
hellomake.h
#ifndef __HELLO_H__
#define __HELLO_H__
void myPrintHelloMake(void);
#endif
The .c files are in the src/ directory and the .h file is in the include/ directory. Makefile compiles the code, creates the obj/ directory, and places and main.o and hellomake.o therein. However, that is where things break down. Here is gcc's complaint:
$ make
mkdir -p obj/
gcc -Wall -g -Iinclude -c src/hellomake.c -o obj/hellomake.o gcc -Wall -g -Iinclude -c src/hellomake.c -o obj/main.o mkdir -p bin/ gcc -o bin/a.out -Wall -g -Iinclude
obj/hellomake.o /usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/10/../../../x86_64-linux-gnu/Scrt1.o: in function `_start': (.text+0x20): undefined reference to `main' collect2: error: ld returned 1 exit status make: *** [Makefile:34: bin/a.out] Error 1
There were a number of issues.
I'd leave off / from (e.g.) BINDIR et. al.
The patsubst was incorrect. It needed $(OBJDIR) in the the TO
Using _OBJS was unnecessary/harmful.
The rule for $(OBJS) was incorrect. It created the two .o files using the first prereq source, so [the function] main was defined twice. It needs a pattern rule instead.
Using $(BINDIR) as a prereq for $(BIN) added bin/ at the end of the gcc line [and it complained]
As M.Oehm mentioned, $< only gets the first prereq.
The all: was indented so it was not recognized properly
Anyway, here's the corrected Makefile:
CC = gcc
BINDIR = bin
OBJDIR = obj
SRCDIR = src
MKDIR = mkdir -p
RM = rm -rf
SRC = $(wildcard $(SRCDIR)/*.c)
###_OBJS = $(patsubst $(SRCDIR)%.c, %.o, $(SRC))
###OBJS = $(addprefix $(OBJDIR), $(_OBJS))
OBJS = $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SRC))
CFLAGS = -Wall -g -Iinclude
_BIN = a.out
BIN = $(addprefix $(BINDIR)/, $(_BIN))
.PHONY: all
all: $(BINDIR) $(OBJDIR) $(BIN)
####$(BIN): $(OBJS) $(BINDIR)
$(BIN): $(OBJS) $(BINDIR)
###$(CC) -o $# $(CFLAGS) $<
$(CC) -o $# $(CFLAGS) $(OBJS)
$(BINDIR):
$(MKDIR) $(BINDIR)
###$(OBJS): $(SRC) $(OBJDIR)
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(CC) $(CFLAGS) -c $< -o $#
$(OBJDIR):
$(MKDIR) $(OBJDIR)
.PHONY: clean
clean:
#echo "Cleaning things up..."
$(RM) $(OBJDIR) $(BINDIR)
I want to create a Makefile for a big C project, with files divided into directories. What I wrote is
CC = gcc
AR = ar
ARFLAGS = rvs
CFLAGS += -std=c99 -Wall -g
INCDIR = ./include
LIBDIR = ./lib
SRCDIR = ./src
BINDIR = ./bin
OBJDIR = ./obj
TESTDIR = ./testfile
INCLUDES = -I.
LDFLAGS = -L/lib
LIBFUNCTIONS = /-lfunctions
LIBTH = -lpthread
LIBUTILITY = /-lutility
OPTFLAGS = -O3 -DNDEBUG
TARGETS = $(BINDIR)/test_functions \
.PHONY: all clean cleanall test1 test2
.SUFFIXES: .c .h
$(BINDIR)/%: $(SRCDIR)/%.c
$(CC) $(CFLAGS) $(INCLUDES) $(OPTFLAGS) -o $# $<
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(CC) $(CFLAGS) $(INCLUDES) $(OPTFLAGS) -c -o $# $<
all : $(TARGETS)
$(BINDIR)/test_functions: $(OBJDIR)/test_functions.o $(LIBDIR)/libutility.a $(LIBDIR)/libfunctions.a
$(CC) $(CFLAGS) $(INCLUDES) $(FLAGS) $(LDFLAGS) -o $# $< $(LIBUTILITY) $(LIBFUNCTIONS)
$(OBJDIR)/test_functions.o: $(SRCDIR)/test_functions.c $(INCDIR)/utility.h $(LIBDIR)/libutility.a $(INCDIR)/functions.h $(LIBDIR)/libfunctions.a
$(CC) $(CCFLAGS) $(INCLUDES) $(FLAGS) -c -o $# $<
$(LIBDIR)/libutility.a: $(OBJDIR)/utility.o $(INCDIR)/utility.h
$(AR) $(ARFLAGS) $# $<
$(LIBDIR)/libfunctions.a: $(OBJDIR)/functions.o $(INCDIR)/functions.h $(INCDIR)/utility.h
$(AR) $(ARFLAGS) $# $<
clean :
rm -f $(TARGETS)
cleanall : clean
\rm -f *.o *~
the problem is that when I try to compile the project using the makefile, the result is
gcc -std=c99 -Wall -g -I. -L/lib -o bin/test_functions obj/test_functions.o -lutility -lfunctions
/usr/bin/ld: impossibile trovare -lutility
/usr/bin/ld: impossibile trovare -lfunctions
collect2: error: ld returned 1 exit status
make: *** [Makefile:54: bin/test_functions] Error 1
it seems that the compiler cannot find the libraries. what can I do to make it work properly?
You have this:
LIBDIR = ./lib
then in your link line you have this:
LDFLAGS = -L/lib
Notice the difference?
Why don't you just say:
LDFLAGS = -L$(LIBDIR)
to avoid repeating yourself (and getting it wrong)?
I´m trying to create a Makefile that build a lib and compile the file. My problem is that depending on the %.c file I need to compile with different lib.
The SRC_MLX need the $(LFLAGS) and the SRC don´t. So the gcc compiler don´t allow me to compile the SRC with the LFLAGS. That´s the reason I need to separate.
I´ve tried this way:
SRCS = $(DIR_SRC)/ft_utils.c \
$(DIR_SRC)/ft_adt.c \
$(DIR_SRC)/ft_circle.c \
$(DIR_SRC)/ft_line.c \
$(DIR_SRC)/ft_trgb.c \
$(DIR_SRC)/ft_quadrilateral.c \
$(DIR_SRC)/ft_player.c \
$(DIR_SRC)/ft_color.c
SRCS_MLX = $(DIR_SRC)/win_update.c \
$(DIR_SRC)/ft_vars.c \
$(DIR_SRC)/ft_image.c \
$(DIR_SRC)/ft_map.c
$(NAME): $(LIB_NAME)
$(CC) $(CFLAGS) main.c -I. -I$(DIR_MLX) -L$(DIR_MLX) -L. $(LFLAGS) $(LIB_FLAG) -o $# -g
$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c
mkdir -p $(DIR_OBJ)
$(CC) $(CFLAGS) -c $< -I. -I$(DIR_MLX) -o $#
$(DIR_OBJ)/$(OBJ_MLX).o: $(DIR_SRC)/$(SRCS_MLX).c
mkdir -p $(DIR_OBJ)
$(CC) $(CFLAGS) -c $< -I. -I$(DIR_MLX) -L$(DIR_MLX) $(LFLAGS) -o $#
$(LIB_NAME): $(OBJ_MLX) LIB_OBJ
$(AR) $(LIB_NAME) $(OBJ)
ranlib $(LIB_NAME)
LIB_OBJ: $(OBJ)
$(AR) $(LIB_NAME) $(OBJ)
In the example above I´ve tried to create a lib with one kind of files and after that create a lib with the first lib with the others files. But I keep getting this error:
Makefile:41: warning: overriding recipe for target '.objs/'
Makefile:37: warning: ignoring old recipe for target '.objs/'
make: Warning: File 'Makefile' has modification time 454 s in the future
rm -f .objs/ft_utils.o .objs/ft_adt.o .objs/ft_circle.o .objs/ft_line.o .objs/ft_trgb.o .objs/ft_quadrilateral.o .objs/ft_player.o .objs/ft_color.o
rm -f libcub3d.a
rm -f main
make: *** No rule to make target 'src/src/win_update.c', needed by '.objs/win_update.o'. Stop.
How can I compile this objects with different lib?
P.S. Those are my variables:
DIR_OBJ = .objs
DIR_SRC = src
DIR_LIB = lib
DIR_MLX = ./minilibx-linux
NAME = main
LIB_NAME = libcub3d.a
OBJ = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS))
OBJ_MLX = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS_MLX))
CC = clang
CFLAGS = -Wall -Werror -Wextra
LFLAGS = -lmlx -lm -lX11 -lXext -lbsd
LIB_FLAG = -lcub3d
AR = ar -rc
RM = rm -f
These lines are definitely not right:
$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c
...
$(DIR_OBJ)/$(OBJ_MLX).o: $(DIR_SRC)/$(SRCS_MLX).c
along with the way you've defined SRCS and SRCS_MLX and these:
OBJ = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS))
OBJ_MLX = $(patsubst $(DIR_SRC)/%.c, $(DIR_OBJ)/%.o, $(SRCS_MLX))
Just expand the variables in the rule in your head, or else ask make to expand it for you with the info function, and you'll see it's definitely not right:
$(info output is '$(DIR_OBJ)/$(OBJ).o: $(DIR_SRC)/$(SRCS).c')
I've got a strange issue when I try to compile my code on my laptop.
It gives me this error: undefined reference to 'main' because apparently it cannot see my source files and then the objects either.
However, the same makefile and code work perfectly on my office machine.
here's the makefile. any hints?
thanks a lot for helping me in advance
ROOT = $(addprefix $(PWD), /)
BUILDS_DIR = $(addprefix $(ROOT), builds/)
SRCS_DIR = $(addprefix $(ROOT), src/)
INCS_DIR = $(addprefix $(ROOT), src/)
OBJS_DIR = $(addprefix $(SRCS_DIR), objects/)
LIBS_DIR = ./
SRCS = $(wildcard $(SRCS_DIR)*.c)
OBJS = $(SRCS:$(SRCS_DIR)%.c=$(OBJS_DIR)%.o)
TARGET = INTERP
EXES = $(addprefix $(BUILDS_DIR), $(TARGET))
CC = gcc
CFLAGS = -Wall -O3 -MD -DTRILIBRARY
INCLUDES = -I$(INCS_DIR)
CL = gcc
LFLAGS =
LIBS = -L$(LIBS_DIR) -lm
RM = rm -f
.PHONY: all $(TARGET) distclean clean
default: clean $(TARGET)
$(TARGET): $(OBJS)
#echo -e "\n\n\t\t*** Compiled $(TARGET) successfully! ***\n" ;
$(CL) $(LFLAGS) -o $(BUILDS_DIR)$# \
$(OBJS) \
$(LIBS)
#echo -e "\n\n\t\t*** Linking $(TARGET) completed! ***\n"
$(OBJS): $(OBJS_DIR)%.o : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $(INCLUDES) \
-c $<\
-o $#
distclean: clean
$(RM) $(EXES)
#echo -e "\n\n\t\t*** Purge $(TARGET) completed! ***\n"
clean:
$(RM) $(OBJS_DIR)*.o \
$(SRCS_DIR)*~
#echo -e "\n\n\t\t*** Cleanup $(TARGET) completed! ***\n"
depend: $(SRCS)
makedepend $(INCLUDES) $^
I am trying to create a Makefile that compiles multiple C files for use in Minix. How would I change the Makefile so that it compiles multiple files at the same time? Below is the current state of my Makefile.
CFLAGS = -D_POSIX_SOURCE
LDFLAGS =
CC = cc
LD = cc
PROG = test
OBJS = test.o
$(PROG): $(OBJS)
$(LD) $(LDFLAGS) $(OBJS) -o $(PROG)
clean:
rm -rf $(PROG) $(OBJS)
I thought I could just list the other programs after PROG and OBJS such as
PROG = test test2
OBJS = test.o test2.o
but that didn't work. Any ideas? Thanks in advance.
Split it up this way:
PROG1 = test
PROG2 = test2
OBJ1 = test.o
OBJ2 = test2.o
$(PROG1): $(OBJ1)
$(LD) $(LDFLAGS) $(OBJ1) -o $(PROG1)
$(PROG2): $(OBJ2)
$(LD) $(LDFLAGS) $(OBJ2) -o $(PROG2)
etc