Something wrong with my ttb_base switching - arm

Question

First ,thanks for the good suggestion from artless noise.
I choose sharing 3G - 4G-1 kernel space address with usr task (vaddr : 0 - 4G) to switch tasks.
I think tasks switching would be like this :
a clock interrupt comes when usr task is running in its own address space
branch to the 3G of usr address space (also it is kernel 3G space).
context saving
schedule ()
{
....
switch_ttb_base (ttb_base); // I think it is the key,(taskA --> TaskB)
// when ttb_base switched,address space is changed,
// it looks like TaskB is interrupted && arrives here.
// So,after context restored,it would return to TaskB
// which looks like TaskB is interrupted just now !
....
}
context restoring
branch to new usr task
So,to share the kernel 3G address ,I should copy the page_tbls from kernel 3G address to usr page_tbls.
Here is my code, (ARM920T,S3C2440)
#define INIT_L1_BASE (0x30100000) /* 16K */
#define INIT_L2_BASE (0x30104000) /* 64k */
#define KERNEL_IMG_SIZE (0x20000) /* 128 K */
#define KERNEL_CODE_START (0xC0000000) /* 3G start */
#define TTB_BASE (0x30000000)
#define PAGE_DIR (TTB_BASE)
#define TTB_FULL_SIZE (0x4000) /* 16K */
#define PAGE_TABLE (TTB_BASE+TTB_FULL_SIZE)
#define PAGE_DIR_SIZE (0x4000) /* 16k */
#define PAGE_TBL_SIZE (0x10000) /* 64K */
void copy_kernel_page_tbls (unsigned dest_ttb,unsigned vaddr,unsigned size)
{
if ((size & 0xFFFFF) || (vaddr & 0xFFFFF)) /* 1M alignment */
panic ( "trying to copy page tables with non-1M alignment !\n" );
volatile unsigned *_from_page_dir,*_to_page_dir;
_from_page_dir = (volatile unsigned *)(TTB_BASE);
_to_page_dir = (volatile unsigned *)dest_ttb;
unsigned l1_idx;
unsigned i = 0,j = 0,k = 0,page;
volatile unsigned *_to_page_tbl,*_from_page_tbl;
for (k = 0 ,size >>= 20 ; k < size ; k ++,vaddr += 0x100000 )
{
l1_idx = vaddr>>20;
if ( !(_from_page_dir[l1_idx] & ~0x3FF))
continue;
if ( !(_to_page_dir[l1_idx] & ~0x3FF) ) { /* if dest page dir unit is empty */
i = l1_idx & ~3;
if ((_to_page_dir[i+0] & ~0x3FF) || (_to_page_dir[i+1] & ~0x3FF)
|| (_to_page_dir[i+2] & ~0x3FF) || (_to_page_dir[i+3] & ~0x3FF) )
{
panic ( "page dir corrupts with l1_idx %d !\n",l1_idx );
}
if (!(page = find_free_page ()))
panic ( "no more free page !\n" ); /* alloc a page page dir*/
wordset ((void*)page,AP_FAULT_ALL|CB|TTB1_SPG,0x1000); /* set all be fault */
_to_page_dir[i+0] = (page + 0x000)|DOMAIN_SYS|TTB0_COARSE; /* small page 1st 1KB */
_to_page_dir[i+1] = (page + 0x400)|DOMAIN_SYS|TTB0_COARSE; /* small page 2nd 1KB */
_to_page_dir[i+2] = (page + 0x800)|DOMAIN_SYS|TTB0_COARSE; /* small page 3rd 1KB */
_to_page_dir[i+3] = (page + 0xC00)|DOMAIN_SYS|TTB0_COARSE; /* small page 4th 1KB */
}
_from_page_tbl = (volatile unsigned*)(_from_page_dir[l1_idx] & ~(0x3FF));
_to_page_tbl = (volatile unsigned*)(_to_page_dir[l1_idx] & ~(0x3FF));
/* continue copying .... */
for (j = 0 ; j < 256 ; j++ ) { /* 256 * 4K */
if (_from_page_tbl[j] & ~0xFFF)
_to_page_tbl[j] = _from_page_tbl[j]; /* FIXME : change attribute */
}
}
}
I call it like this
copy_kernel_page_tbls (INIT_L1_BASE,KERNEL_CODE_START,1<<30); /* 1G size */
the clock handler is
extern unsigned long __ticks;
#define __DEBUG__
static
void schedlue ( void )
{
// ..............
sync_dcaches ();
invalidate_icaches ();
invalidate_dcaches ();
invalidate_tlbs();
set_ttb_base(current_p->ttb_base);
}
void __do_timer0 (void)
{
static unsigned i = 0;
++ i;
current_p = task_st[i & 1]; /* just 2 tasks */
__ticks ++;
.....
.....
schedule ();
}
ARM just halt.I don't know why ? Any help appreciated !

Answer 1

I did a mmu test to test mmu cache operations
I switch ttb base with :
void change_ttb_base (unsigned ttb)
{
sync_dcaches ();
invalidate_icache ();
invalidate_dcaches ();
set_ttb_base (ttb);
invalidate_tlbs ();
}
on my s3c2440 board ,0x30000000 - 0x34000000 is the sdram address,I do the test on sdram address space,
ttb_base switched successfully!
but when the code run at the high 3G address ,after I called change_ttb_base (),ARM just halt.I guess,the code running in high 3G address need MMU address translation,I changed ttb_base and invalidate all i & d cache and tlbs ,so ARM core don't know what the next step is ,so just halt .....
Is that right ???