I am trying to compile my project after adding a new source(processHandling.c) and I am getting this as a result when I 'make'
gcc -gstabs -W -Wall -std=gnu99 -c main.c
gcc -gstabs -W -Wall -std=gnu99 -c inputHandling.c
gcc -gstabs -W -Wall -std=gnu99 -c syscallsWrapper.c
gcc -gstabs -W -Wall -std=gnu99 -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
gcc: error: processHandling.o: No such file or directory
make: *** [myShell] Error 1
This is the makefile
CC = gcc
CFLAGS = -gstabs -W -Wall -std=gnu99
myShell: main.o inputHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
main.o: main.c
$(CC) $(CFLAGS) -c main.c
inputHandling.o: inputHandling.c
$(CC) $(CFLAGS) -c inputHandling.c
processHandling.o: processHandling.c
$(CC) $(CFLAGS) -c processHandling.c
syscallsWrapper.o: syscallsWrapper.c
$(CC) $(CFLAGS) -c syscallsWrapper.c
clean:
-rm myShell *.o
I tried running make with the -d flag and it seems make for some reason is totally ignoring the rule to compile processHandling.o; what could the problem be?
Also note that if I compile processHandling manually using gcc -c everything works fine.
Add processHandling.o to the dependency list for the myShell target:
myShell: main.o inputHandling.o processHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
By the way, using automatic variables can help reduce the repeated file names. For example:
myShell: main.o inputHandling.o processHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o $# $^
You need to add "processHandling.o" as a prerequisit of myShell. Otherwise when making myShell, the rule for processHandling.o will not be applied because the makefile thinks that that processHandling.o is not needed for myShell. You can simply add it like this
myShell: main.o inputHandling.o syscallsWrapper.o processHandling.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
Check if you really have the file processHandling.c. This error implies that the source file has not been found.
Related
I am new to c programming, and I am having a problem with making Makefile for it.
I did like
CC = gcc
CFLAGS = -fsanitize=address -g -Wall -Wvla
OUTPUT = prac
all: $(OUTPUT)
mymalloc.o: mymalloc.c mymalloc.h
$(CC) $(CFLAGS) -c $# mymalloc.c
%: %.c
$(CC) $(CFLAGS) -o $# mymalloc.o $^
and I try to make file with just typing "make"
But it keep says
gcc -fsanitize=address -g -Wall -Wvla -o prac mymalloc.o prac.c
clang: error: no such file or directory: 'mymalloc.o'
make: *** [prac] Error 1
whenever I try to make it , did I do something wrong?
Thank you.
Edit)
I got it right with using this!
CC = gcc
CFLAGS = -fsanitize=address -g -Wall -Wvla
DEPS = mymalloc.h
OBJS = prac.o mymalloc.o
%.o: %.c $(DEPS)
$(CC) $(CFLAGS) -c -o $# $<
prac: $(OBJS)
$(CC) $(CFLAGS) -o $# $^
You need to make the executable dependent on mymalloc.o:
%: %.c mymalloc.o
$(CC) $(CFLAGS) -o $# mymalloc.o $^
The dependency tells make that it needs to execute the rule for creating mymalloc.o.
Also your rule for making mymalloc.o is wrong. You need -o before $#:
mymalloc.o: mymalloc.c mymalloc.h
$(CC) $(CFLAGS) -c -o $# mymalloc.c
Otherwise it's trying to use the output file as one of the input files.
I want to compile a C program from GitHub on Windows 7 and get an error that a file is not found. I have installed MinGW Make and its dependancies. I think maybe this program is only intended to run on Linux.
The Console output:
E:\work-c\iso2opl-clone\iso2opl>make
gcc -std=gnu99 -pedantic -usr\include -usr\local\inc
lude -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE -c isofs.c -o isofs.o
process_begin: CreateProcess(NULL, gcc -std=gnu99 -pedantic -F:\programs\mingw\i
nclude -F:\programs\mingw\local\include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SO
URCE -c isofs.c -o isofs.o, ...) failed.
make (e=2): Le fichier spécifié est introuvable.
make: *** [isofs.o] Erreur 2
the makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -I/usr/include -I/usr/local/include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE
#CFLAGS += -DDEBUG
ifeq ($(_WIN32),1)
CFLAGS += -D_WIN32
endif
OBJS = isofs.o \
iso2opl.o
all: $(TARGET)
rm-elf:
-rm -f $(TARGET) $(OBJS)
$(TARGET): $(OBJS)
$(CC) $(OBJS) -o $(TARGET) $(LIBS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%.o: %.cpp
$(CC) $(CFLAGS) -c $< -o $#
clean:
rm -r $(OBJS) $(TARGET)
I don't know maybe the paths are wrongs.
Best Regards
Try to run the make in the MSYS2 shell (https://www.msys2.org/). I was able to build the sources from https://github.com/arcadenea/iso2opl without issue.
I have a makefile, but it seems like the cflags are only working for certain files in my program, and I am not sure why.
Here is what happens when I use make:
$ make
gcc -Wall -ansi -pedantic -g -c main.c
gcc -c fw.c
gcc -c trie.c
gcc -Wall -ansi -pedantic -g -c linked.c
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
You can see that when trying to make fw.c and trie.c it doesn't include the flags, but it does include the flags for the other files.
Here is my makefile:
CC = gcc
CFLAGS = -Wall -ansi -pedantic -g
MAIN = main
OBJS = main.o fw.o trie.o linked.o
all : $(MAIN)
$(MAIN) : $(OBJS) fw.h trie.h linked.h
$(CC) $(CFLAGS) -o fw $(OBJS)
main.o : main.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c main.c
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
linked.o : linked.c trie.h linked.h
$(CC) $(CFLAGS) -c linked.c
rm :
rm *.o $(MAIN) core
I also have an additional problem in that whenever I use make with unchanged files from the last make, it still executes this line:
$ make
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
Whereas usually, it gives me the message "nothing to be done for all". I have tried to compare this makefile to my other working makefiles, but I can't find the error(s). Where have I gone wrong?
You have typos in your Makefile:
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
Note the G. Instead, use this:
fw.o : fw.c fw.h trie.h
$(CC) $(CFLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c trie.c
I'm trying to get a small project compiled but am getting this error, I've been searching around and people get this error mainly because of incorrect file extension, but I don't really think that's the cause here:
gcc -c -W -Wall -ggdb -I. router.c -o router.o
router.c:106: warning: unused parameter ‘hname’
router.c: In function ‘flood_neighbors’:
router.c:464: warning: unused variable ‘bytes_rcvd’
router.c: At top level:
router.c:536: warning: unused parameter ‘fd’
gcc -c -W -Wall -ggdb -I. link_info.h -o link_info.o
gcc -c -W -Wall -ggdb -I. route.h -o route.o
gcc -c -W -Wall -ggdb -I. sequence.h -o sequence.o
gcc -W -Wall -ggdb -I. router.o link_info.o route.o sequence.o -o router
link_info.o: file not recognized: File format not recognized
collect2: ld returned 1 exit status
make: *** [router] Error 1
and my make file looks like:
CC = gcc
INC = -I.
FLAGS = -W -Wall -ggdb
router: router.o link_info.o route.o sequence.o
$(CC) $(FLAGS) $(INC) $^ -o $#
router.o: router.c
$(CC) -c $(FLAGS) $(INC) $< -o $#
sequence.o: sequence.h sequence.h
$(CC) -c $(FLAGS) $(INC) $< -o $#
link_info.o: link_info.h link_info.c
$(CC) -c $(FLAGS) $(INC) $< -o $#
route.o: route.h route.c
$(CC) -c $(FLAGS) $(INC) $< -o $#
What I'm confused on is the rules for three object files are of the same format, but why only the link one yells? Thanks a lot!
I would like to suggest few edits in your makefile.
CC = gcc
INC = -I.
FLAGS = -W -Wall -ggdb
router: router.o link_info.o route.o sequence.o
$(CC) $(FLAGS) $(INC) $^ -o $#
router.o: router.c
$(CC) -c $(FLAGS) $(INC) $< -o $#
sequence.o: sequence.h sequence.h //Where is the c file ?
$(CC) -c $(FLAGS) $(INC) $< -o $#
link_info.o: link_info.h link_info.c //Change the order. Put c file first and then the header
$(CC) -c $(FLAGS) $(INC) $< -o $#
route.o: route.h route.c //Same as above
$(CC) -c $(FLAGS) $(INC) $< -o $#
With recent versions of make you can remove all the object rules because make uses a default rule to build an object from .c or .cpp files. Just leave the rule to build the final executable in place.
For example, change the file so it contains this line only:
router: router.o link_info.o route.o sequence.o
$(CC) $(FLAGS) $(INC) $^ -o $#
Move link_info.o to the end of the list in the router: dependencies and I suspect you'll blow up on route.o instead.
You seem to be compiling a headers as C files. I have no idea what GCC does in that case. In your makefile rules, the .c file must be the first dependency if you are going to use $< to generate the source file to compile.
The link_info: and route: rules have the .c and .h files reversed and the sequence: rule lists the .h file twice!
I need to write a simple make file for my.c, and so after
make
then my program can be run by
./my
my.c can be compiled by this:
gcc cJ/cJ.c my.c -lcrypto -o my -lm
Thanks
I put this in my makefile
all:my
my: cJ.o my.o
gcc cJ.o -lcrypt my.o -o my
cJ.o: cJ/cJ.c
gcc -c cJ/cJ.c
my.o: my.c
gcc -c my.c -lm
help please
Well, makefiles are just kind of special scripts. Every is unique, for such simple task this would be sufficient:
Makefile:
CC=gcc
CFLAGS=-lm -lcrypto
SOURCES=my.c cJ/cJ.c
all: my
my: $(SOURCES)
$(CC) -o my $(SOURCES) $(CFLAGS)
Later you may want to use some other options such as wildcards %.c to compile in multiple files without having to write them in.
Alternatively:
CC=gcc
CFLAGS=-lm -lcrypto
MY_SOURCES = my.c cJ/cJ.c
MY_OBJS = $(patsubst %.c,%.o, $(MY_SOURCES))
all: my
%o: %.c
$(CC) $(CFLAGS) -c $<
my: $(MY_OBJS)
$(CC) $(CFLAGS) $^ -o $#
Note that lines following each target ("my:", ...) must start with tab (\t), not spaces.
Just a minor correction: put the -lm to the linking step, and there after all object files.
all: my
my: cJ.o my.o
gcc cJ.o my.o -o my -lcrypt -lm
cJ.o: cJ/cJ.c
gcc -c cJ/cJ.c
my.o: my.c
gcc -c my.c
And then, you could work more with automatic variables:
all: my
my: cJ.o my.o
gcc $^ -o $# -lcrypt -lm
cJ.o: cJ/cJ.c
gcc -c $^
my.o: my.c
gcc -c $^
where $# is the target of the current rule and $^ are the prerequisites.
See also http://www.gnu.org/software/make/manual/make.html.
simple make file for your program is
build :
gcc /your_full_path_to_c_file/cJ.c my.c -lcrypto -o my -lm
just copy this in one file keep name of that file as makefile
then run as make build