I have a makefile, but it seems like the cflags are only working for certain files in my program, and I am not sure why.
Here is what happens when I use make:
$ make
gcc -Wall -ansi -pedantic -g -c main.c
gcc -c fw.c
gcc -c trie.c
gcc -Wall -ansi -pedantic -g -c linked.c
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
You can see that when trying to make fw.c and trie.c it doesn't include the flags, but it does include the flags for the other files.
Here is my makefile:
CC = gcc
CFLAGS = -Wall -ansi -pedantic -g
MAIN = main
OBJS = main.o fw.o trie.o linked.o
all : $(MAIN)
$(MAIN) : $(OBJS) fw.h trie.h linked.h
$(CC) $(CFLAGS) -o fw $(OBJS)
main.o : main.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c main.c
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
linked.o : linked.c trie.h linked.h
$(CC) $(CFLAGS) -c linked.c
rm :
rm *.o $(MAIN) core
I also have an additional problem in that whenever I use make with unchanged files from the last make, it still executes this line:
$ make
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
Whereas usually, it gives me the message "nothing to be done for all". I have tried to compare this makefile to my other working makefiles, but I can't find the error(s). Where have I gone wrong?
You have typos in your Makefile:
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
Note the G. Instead, use this:
fw.o : fw.c fw.h trie.h
$(CC) $(CFLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c trie.c
Related
When I compile my code on the command line, there are no problems:
$ gcc -Wall -O2 -o mess main.c getmatrix.c toktoint.c prtmatrix.c getdist.c
But when I compile via make, it fails:
$ make clean
$ make
/usr/bin/gcc -O2 -Wall -c toktoint.c -o toktoint.o
/usr/bin/gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
/usr/bin/gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
/usr/bin/gcc -O2 -Wall -c getdist.c -o getdist.o
/usr/bin/gcc -O2 -Wall -c -o main.o main.c
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
/usr/lib/gcc/x86_64-pc-cygwin/10/../../../../x86_64-pc-cygwin/bin/ld: /usr/lib/gcc/x86_64-pc-cygwin/10/../../../../lib/libcygwin.a(libcmain.o): in function `main':
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37: undefined reference to `WinMain'
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37:(.text.startup+0x82): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `WinMain'
collect2: error: ld returned 1 exit status
make: *** [Makefile:44: mess] Error 1
Here is my Makefile:
CC=/usr/bin/gcc
OPTIMIZATION=2
CFLAGS=-O$(OPTIMIZATION) -Wall
LFLAGS=
TARGET=mess
OBJECTS=toktoint.o \
getmatrix.o \
prtmatrix.o \
getdist.o \
main.o
SOURCES=toktoint.c \
getmatrix.c \
prtmatrix.c \
getdist.c \
main.c
HEADERS=getmatrix.h \
toktoint.h \
prtmatrix.h \
getdist.h
all: $(TARGET)
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $<
%.o: %.c %.h
$(CC) $(CFLAGS) -c $< -o $#
clean:
#rm -f $(OBJECTS) $(TARGET)
I tried changing various flags, such as "-m64". And other suggestions which I found on stackoverflow, but no success.
If I compile each module on the command line, it also works:
$ make clean
$ gcc -O2 -Wall -c toktoint.c -o toktoint.o
$ gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
$ gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
$ gcc -O2 -Wall -c getdist.c -o getdist.o
$ gcc -O2 -Wall -c main.c -o main.o
$ gcc -Wall -O2 -o mess main.o getdist.o getmatrix.o prtmatrix.o toktoint.o
So it appears the problem is with make or Makefile.
Look at the output from make again, especially the linker line:
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
It does not build with all the object files. Most notably, it misses main.o which I assume contains your main function.
The variable $< is only
The name of the first prerequisite
(from this make manual, emphasis mine).
To get all prerequisites (all object files) use $^:
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $^
I wrote the following makefile:
CC = gcc
OBJS = Car.o Guide.o GuideSystem.o
DEBUG_OBJS = Car_debug.o Guide_debug.o GuideSystem_debug.o
SOURCE = Car.c Guide.c GuideSystem.c
HEADER = Car.h Guide.h GuideSystem.h list.h set.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror
LIBM = -L. -lib
EXEC = test.exe test1.exe test2.exe test2_debug.exe
TEST_O = test1.o test2.o test2_debug.o test.o
#make test1.exe
test1.exe : $(OBJS) test1.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test1.o $(LIBM) -o $#
#make test2.exe
test2.exe : $(OBJS) test2.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test2.o $(LIBM) -o $#
#make test2_debug.exe
test2_debug.exe : $(OBJS) test2_debug.o
$(CC) $(CFLAGS) -g $(OBJS) test2_debug.o $(LIBM) -o $#
#make test.exe
test.exe : $(OBJS) test.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test.o $(LIBM) -o $#
#Testing (no asserts)
test.o : test.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test1.o : test1.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test2.o : test2.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Guide.o : Guide.c Guide.h list.h Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
GuideSystem.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Car.o : Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
#Debug testing
test2_debug.o : test2.c Guide.h GuideSystem.h
$(CC) -c -g $(CFLAGS) test2.c -o $#
Guide_debug.o : Guide.c Guide.h list.h Car.h
$(CC) -c -g $(CFLAGS) Guide.c -o $#
GuideSystem_debug.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -g $(CFLAGS) GuideSystem.c -o $#
Car_debug.o : Car.h
$(CC) -c -g $(CFLAGS) Car.c -o $#
#Clean builds
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(TEST_O)
When I run make test I get:
gcc test.o -o test
test.o: In function `main':
test.c:(.text+0x29): undefined reference to `createGuide'
... more undefined functions
I have some problem with the makefile but I can't seem to find the problem. All of the other make options work properly, only make test fails.
As I understand it should run:
gcc -c -DNDEBUG -std=c99 -Wall -Werror -pedantic-errors test.c
gcc -o test.exe -DNDEBUG Guide.o GuideSystem.o Car.o test.o -L. -lib
What could be the problem? How can I solve it? Do I have a problem with my makefile?
You didn't define any test target, so make guessed wrongly that you wanted to make a program named test just from test.o (implicit rule).
What you should probably insert in Makefile is:
test: test.exe test2.exe
./test.exe
./test2.exe
.PHONY: test
This is my first post in this forum. Sorry for bothering but I've been looking for something similar and strangely I couldn't find it. Here's the issue.
I have three (main) files with no headers and I want to compile them either at once (if I simply type "make") or one by one (if I specify the name of the file with no extension). So I built my makefile but something is wrong in the command
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
where I got this error
make: *** No rule to make target....
here's the complete file
.SUFFIXES: .c
ROOT = $(addprefix $(PWD), /)
BUILDS_DIR = $(addprefix $(ROOT), builds/)
SRCS_DIR = $(addprefix $(ROOT), src/)
SRCS = $(wildcard $(SRCS_DIR)*.c)
TARGETS = ${SRCS:$(SRCS_DIR)%.c=%}
EXES = ${addprefix $(BUILDS_DIR), $(TARGETS)}
CC = gcc
CFLAGS = -Wall -O3
RM = rm -f
.PHONY: all $(TARGETS) clean
all: $(TARGETS)
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) \
$< \
-o $#
#echo -e "\n\n\t\t*** Compile successfully! ***\n" ;
clean:
$(RM) $(EXES) \
$(SRCS_DIR)*~
#echo -e "\n\n\t\t*** Cleanup complete! ***\n"
Where am I wrong? I guess the answer is very silly and probably based on a basic error.
thanks in advance
Assuming GNU Make (since you use its syntax).
The, or the first, problem is that you are trying to rewrite the target static pattern incorrectly, by trying to concatenate the target directory to the pattern, rather than simply using the target's filename.
You had:
$(TARGETS): $(BUILDS_DIR)% : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $#
The solution is to use add the directory path on the command line
$(TARGETS): % : $(SRCS_DIR)%.c
$(CC) $(CFLAGS) $< -o $(BUILDS_DIR)$#
Lets assume that your three source files are file1.c, file2.c and file3.c. I would created the makefile to look like this (assuming GNU make)
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
file1 : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
file2 : file2.c
$(CC) $(CFLAGS) -c file2.c -o file2.o
file3 : file3.c
$(CC) $(CFLAGS) -c file3.c -o file3.o
clean :
$(RM) *.o $(PROG) *.*~
A sample using this make file is (I use the -n to show what rules would be run, but not actually run them because my source files are empty files for testing.)
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file1
gcc -ansi -Wall -pedantic -c file1.c -o file1.o
We can shorten the above make file my making use of wild-cards;
CC = gcc
CFLAGS = -ansi -Wall -pedantic
RM = rm -f
OBJS = file1.o file2.o file3.o
PROG=my_program
$(PROG) : $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
all : clean $(PROG)
% : %.c
$(CC) $(CFLAGS) -c $< -o $#.o
clean :
$(RM) *.o $(PROG) .~
We need to append a '.o' to the output file name so that we are creating files in the format defined by the $(OBJ) variable of the first build rule works correctly. Doing this gives the following example runs:
[******#broadsword junk]$ make -n
gcc -ansi -Wall -pedantic -c -o file1.o file1.c
gcc -ansi -Wall -pedantic -c -o file2.o file2.c
gcc -ansi -Wall -pedantic -c -o file3.o file3.c
gcc -ansi -Wall -pedantic file1.o file2.o file3.o -o my_program
[******#broadsword junk]$ make -n file2
gcc -ansi -Wall -pedantic -c file2.c -o file2.o
BTW, I personally don't mind typing an extra two characters and I like having my target match the output of the set of rules that get run, so I would write the rules as either
file1.o : file1.c
$(CC) $(CFLAGS) -c file1.c -o file1.o
or
%.o :%.c
$(CC) $(CFLAGS) -c $< -o $#
Finally I strongly suspect that when we execute make or make all, we are not running the file-specific rules in the lower part of the makefile, rather we are running the the built in rule described in the GNU manual as: "n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c".
I am trying to compile my project after adding a new source(processHandling.c) and I am getting this as a result when I 'make'
gcc -gstabs -W -Wall -std=gnu99 -c main.c
gcc -gstabs -W -Wall -std=gnu99 -c inputHandling.c
gcc -gstabs -W -Wall -std=gnu99 -c syscallsWrapper.c
gcc -gstabs -W -Wall -std=gnu99 -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
gcc: error: processHandling.o: No such file or directory
make: *** [myShell] Error 1
This is the makefile
CC = gcc
CFLAGS = -gstabs -W -Wall -std=gnu99
myShell: main.o inputHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
main.o: main.c
$(CC) $(CFLAGS) -c main.c
inputHandling.o: inputHandling.c
$(CC) $(CFLAGS) -c inputHandling.c
processHandling.o: processHandling.c
$(CC) $(CFLAGS) -c processHandling.c
syscallsWrapper.o: syscallsWrapper.c
$(CC) $(CFLAGS) -c syscallsWrapper.c
clean:
-rm myShell *.o
I tried running make with the -d flag and it seems make for some reason is totally ignoring the rule to compile processHandling.o; what could the problem be?
Also note that if I compile processHandling manually using gcc -c everything works fine.
Add processHandling.o to the dependency list for the myShell target:
myShell: main.o inputHandling.o processHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
By the way, using automatic variables can help reduce the repeated file names. For example:
myShell: main.o inputHandling.o processHandling.o syscallsWrapper.o
$(CC) $(CFLAGS) -o $# $^
You need to add "processHandling.o" as a prerequisit of myShell. Otherwise when making myShell, the rule for processHandling.o will not be applied because the makefile thinks that that processHandling.o is not needed for myShell. You can simply add it like this
myShell: main.o inputHandling.o syscallsWrapper.o processHandling.o
$(CC) $(CFLAGS) -o myShell main.o inputHandling.o processHandling.o syscallsWrapper.o
Check if you really have the file processHandling.c. This error implies that the source file has not been found.
I have a small problem, and I have tried everything to test this function, could you please help me? I need to write a C file that is called "mutual_info.c", and it needs a mathematical function. I have included the library and linked it in the makefile, but it still gives me "undefined reference to log"... my includes look like this: (I'm using Eclipse on Ubuntu)
#include <stdio.h>
#include <stdlib.h>
#include "sample.h"
#include "graph_or.h"
#include <math.h>
and my makefile looks like this:
all:
gcc -g amostra.c sample.h -o amostra.o
gcc -g graph_or.c graph_or.h -o graph_or.o
gcc -g graph_w.c graph_W.h -o graph_W.o
gcc -g mutual_info.c -o mutual_info.o -lm
clean:
rm *.o
I have absolutely no idea what is going on, I have even tried to define the LDFLAGS before the command "all" and putting it like this:
LDFLAGS= -lm
all:
gcc -g amostra.c sample.h -o amostra.o
gcc -g graph_or.c graph_or.h -o graph_or.o
gcc -g graph_w.c graph_W.h -o graph_W.o
gcc -g mutual_info.c -o mutual_info.o -lm
clean:
rm *.o
But it still won't work!! Please anyone, I need help with this! Thanks!
Let's take this in steps.
The usual way to write a makefile is to have a rule for each target, and to use prerequisites:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g amostra.o graph_or.o graph_w.o mutual_info.o -o thing -lm
mutual_info.o: mutual_info.c
gcc -g -c mutual_info.c -o mutual_info.o -lm
amostra.o: amostra.c sample.h
gcc -g -c amostra.c -o amostra.o
graph_or.o: graph_or.c graph_or.h
gcc -g -c graph_or.c -o graph_or.o
graph_w.o: graph_w.c graph_w.h
gcc -g -c graph_w.c -o graph_w.o
mutual_info.o: mutual_info.c
gcc -g -c mutual_info.c -o mutual_info.o -lm
(I have guessed that you want the executable to be called thing, and that you meant graph_w, not graph_W.)
That should work, but we can make it tidier. First we introduce automatic variables:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g $^ -o $# -lm
mutual_info.o: mutual_info.c
gcc -g -c $< -o $#
amostra.o: amostra.c sample.h
gcc -g -c $< -o $#
graph_or.o: graph_or.c graph_or.h
gcc -g -c $< -o $#
graph_w.o: graph_w.c graph_w.h
gcc -g -c $< -o $#
mutual_info.o: mutual_info.c
gcc -g -c $< -o $#
Then we see that these recipes use the same command, so we create a pattern rule:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g $^ -o $# -lm
amostra.o: sample.h
graph_or.o: graph_or.h
graph_w.o: graph_w.h
%.o: %.c
gcc -g -c $< -o $#
Give this a try and tell us if it works.
Is that a snippet from your Makefile? Hav you tried exporting LDFLAGs? I have seen this error before, but it was always fixed with the -lm flag.
gcc -lm -o blah blah.c
you need to:
gcc -c -o amostra.o amostra.c
gcc -c -o graph_or.o graph_or.c
gcc -c -o graph_w.o graph_w.c
gcc -c -o mutual_info.o mutual_info.c
gcc -o YourExecutableName amostra.o graph_or.o graph_w.o mutual_info.o -lm
Here's a generic makefile using my best guess of what you want to achieve: It compiles all *.c files in the current directory and creates a binary mutual_info.
RM := rm -f
CC := gcc
CFLAGS := -g
LDLIBS := -lm
SOURCES := $(wildcard *.c)
OBJECTS := $(SOURCES:%.c=%.o)
DEPS := $(SOURCES:%.c=%.d)
BINARY := mutual_info
FILES_TO_CLEAN := $(OBJECTS) $(DEPS)
.PHONY : all clean realclean
all : $(BINARY)
clean :
$(RM) $(FILES_TO_CLEAN)
realclean : FILES_TO_CLEAN += $(BINARY)
realclean : clean
-include $(DEPS)
$(OBJECTS) : %.o : %.c
$(CC) $(CFLAGS) -c -MMD -o $# $<
$(BINARY) : $(OBJECTS)
$(CC) -o $# $^ $(LDLIBS)
Please clarify if that's not what you want.