math.h linkage with file - c

I have a small problem, and I have tried everything to test this function, could you please help me? I need to write a C file that is called "mutual_info.c", and it needs a mathematical function. I have included the library and linked it in the makefile, but it still gives me "undefined reference to log"... my includes look like this: (I'm using Eclipse on Ubuntu)
#include <stdio.h>
#include <stdlib.h>
#include "sample.h"
#include "graph_or.h"
#include <math.h>
and my makefile looks like this:
all:
gcc -g amostra.c sample.h -o amostra.o
gcc -g graph_or.c graph_or.h -o graph_or.o
gcc -g graph_w.c graph_W.h -o graph_W.o
gcc -g mutual_info.c -o mutual_info.o -lm
clean:
rm *.o
I have absolutely no idea what is going on, I have even tried to define the LDFLAGS before the command "all" and putting it like this:
LDFLAGS= -lm
all:
gcc -g amostra.c sample.h -o amostra.o
gcc -g graph_or.c graph_or.h -o graph_or.o
gcc -g graph_w.c graph_W.h -o graph_W.o
gcc -g mutual_info.c -o mutual_info.o -lm
clean:
rm *.o
But it still won't work!! Please anyone, I need help with this! Thanks!

Let's take this in steps.
The usual way to write a makefile is to have a rule for each target, and to use prerequisites:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g amostra.o graph_or.o graph_w.o mutual_info.o -o thing -lm
mutual_info.o: mutual_info.c
gcc -g -c mutual_info.c -o mutual_info.o -lm
amostra.o: amostra.c sample.h
gcc -g -c amostra.c -o amostra.o
graph_or.o: graph_or.c graph_or.h
gcc -g -c graph_or.c -o graph_or.o
graph_w.o: graph_w.c graph_w.h
gcc -g -c graph_w.c -o graph_w.o
mutual_info.o: mutual_info.c
gcc -g -c mutual_info.c -o mutual_info.o -lm
(I have guessed that you want the executable to be called thing, and that you meant graph_w, not graph_W.)
That should work, but we can make it tidier. First we introduce automatic variables:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g $^ -o $# -lm
mutual_info.o: mutual_info.c
gcc -g -c $< -o $#
amostra.o: amostra.c sample.h
gcc -g -c $< -o $#
graph_or.o: graph_or.c graph_or.h
gcc -g -c $< -o $#
graph_w.o: graph_w.c graph_w.h
gcc -g -c $< -o $#
mutual_info.o: mutual_info.c
gcc -g -c $< -o $#
Then we see that these recipes use the same command, so we create a pattern rule:
thing: amostra.o graph_or.o graph_w.o mutual_info.o
gcc -g $^ -o $# -lm
amostra.o: sample.h
graph_or.o: graph_or.h
graph_w.o: graph_w.h
%.o: %.c
gcc -g -c $< -o $#
Give this a try and tell us if it works.

Is that a snippet from your Makefile? Hav you tried exporting LDFLAGs? I have seen this error before, but it was always fixed with the -lm flag.
gcc -lm -o blah blah.c

you need to:
gcc -c -o amostra.o amostra.c
gcc -c -o graph_or.o graph_or.c
gcc -c -o graph_w.o graph_w.c
gcc -c -o mutual_info.o mutual_info.c
gcc -o YourExecutableName amostra.o graph_or.o graph_w.o mutual_info.o -lm

Here's a generic makefile using my best guess of what you want to achieve: It compiles all *.c files in the current directory and creates a binary mutual_info.
RM := rm -f
CC := gcc
CFLAGS := -g
LDLIBS := -lm
SOURCES := $(wildcard *.c)
OBJECTS := $(SOURCES:%.c=%.o)
DEPS := $(SOURCES:%.c=%.d)
BINARY := mutual_info
FILES_TO_CLEAN := $(OBJECTS) $(DEPS)
.PHONY : all clean realclean
all : $(BINARY)
clean :
$(RM) $(FILES_TO_CLEAN)
realclean : FILES_TO_CLEAN += $(BINARY)
realclean : clean
-include $(DEPS)
$(OBJECTS) : %.o : %.c
$(CC) $(CFLAGS) -c -MMD -o $# $<
$(BINARY) : $(OBJECTS)
$(CC) -o $# $^ $(LDLIBS)
Please clarify if that's not what you want.

Related

How to link math.h library in a makefile?

i need to compile 3 files- part1.c, part2.c, and part3.c in a makefile.
only part3.c needs to use the <math.h> library.
Before a makefile, this is what the gcc commands will look like:
gcc -g -o part1 part1.c
gcc -g -o part2 part2.c
gcc -g -o part3 part3.c -lm
When i try to use a makefile to run the "make" command, i keep getting errors and it does not recognize any of the math functions from the math.h library.
This is what i have in my makefile so far that is not working:
CC = gcc
CFLAGS = -Wall -g
all: driver1
clean:
rm -f *.o driver1
part1.o: part1.c
$(CC) $(CFLAGS) -c part1.c
part2.o: part2.c
$(CC) $(CFLAGS) -c part2.c
part3.o: part3.c
$(CC) $(CFLAGS) -c part3.c -lm
driver1: part1.o part2.o part3.o
$(CC) $(CFLAGS) -o driver1 part1.o part2.o part3.o
i had tried to run the makefile i provided, but it was giving me errors. any help will be appreciated
part3.o does not need to link with the library although it uses its header file. You need the library when linking everything into driver1:
# ...
part3.o: part3.c
$(CC) $(CFLAGS) -c part3.c
driver1: part1.o part2.o part3.o
$(CC) $(CFLAGS) -o driver1 part1.o part2.o part3.o -lm

R_X86_64_PC32 against undefined symbol `WinMain' on cygwin

When I compile my code on the command line, there are no problems:
$ gcc -Wall -O2 -o mess main.c getmatrix.c toktoint.c prtmatrix.c getdist.c
But when I compile via make, it fails:
$ make clean
$ make
/usr/bin/gcc -O2 -Wall -c toktoint.c -o toktoint.o
/usr/bin/gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
/usr/bin/gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
/usr/bin/gcc -O2 -Wall -c getdist.c -o getdist.o
/usr/bin/gcc -O2 -Wall -c -o main.o main.c
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
/usr/lib/gcc/x86_64-pc-cygwin/10/../../../../x86_64-pc-cygwin/bin/ld: /usr/lib/gcc/x86_64-pc-cygwin/10/../../../../lib/libcygwin.a(libcmain.o): in function `main':
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37: undefined reference to `WinMain'
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37:(.text.startup+0x82): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `WinMain'
collect2: error: ld returned 1 exit status
make: *** [Makefile:44: mess] Error 1
Here is my Makefile:
CC=/usr/bin/gcc
OPTIMIZATION=2
CFLAGS=-O$(OPTIMIZATION) -Wall
LFLAGS=
TARGET=mess
OBJECTS=toktoint.o \
getmatrix.o \
prtmatrix.o \
getdist.o \
main.o
SOURCES=toktoint.c \
getmatrix.c \
prtmatrix.c \
getdist.c \
main.c
HEADERS=getmatrix.h \
toktoint.h \
prtmatrix.h \
getdist.h
all: $(TARGET)
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $<
%.o: %.c %.h
$(CC) $(CFLAGS) -c $< -o $#
clean:
#rm -f $(OBJECTS) $(TARGET)
I tried changing various flags, such as "-m64". And other suggestions which I found on stackoverflow, but no success.
If I compile each module on the command line, it also works:
$ make clean
$ gcc -O2 -Wall -c toktoint.c -o toktoint.o
$ gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
$ gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
$ gcc -O2 -Wall -c getdist.c -o getdist.o
$ gcc -O2 -Wall -c main.c -o main.o
$ gcc -Wall -O2 -o mess main.o getdist.o getmatrix.o prtmatrix.o toktoint.o
So it appears the problem is with make or Makefile.
Look at the output from make again, especially the linker line:
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
It does not build with all the object files. Most notably, it misses main.o which I assume contains your main function.
The variable $< is only
The name of the first prerequisite
(from this make manual, emphasis mine).
To get all prerequisites (all object files) use $^:
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $^

What is the correct or efficient form to write a Makefile when you need two executables that use the same library?

I'm trying to write a Makefile to compile two programs that include the same .h (also mine), but with my actual Makefile if I type "make" in command line twice in a row, I don't get "bla bla is up to date", it recompile part of the stuff when it's not necessary. Any way to do this in a more efficient form?
Context
producer.c and consumer.c #include random_numbers.h in order to generate random numbers to its functions.
My Makefile
CC = gcc
FLAGS = -Wall -g
LIBS = -lrt -lpthread
HEADER_FILES_DIR = .
INCLUDES = -I $(HEADER_FILES_DIR)
SRCS = e1_producer.c e1_consumer.c $(HEADER_FILES_DIR)/random_num.c
OBJ = $(SRC:.c=.co)
DEPS = $(HEADER_FILES_DIR)/random_num.h
all: e1_producer e1_consumer
random_num.o: random_num.c random_num.h
$(CC) $(FLAGS) -c random_num.c
e1_producer: e1_producer.o random_num.o
$(CC) $(FLAGS) -o producer e1_producer.o random_num.o $(LIBS)
e1_producer.o: e1_producer.c
$(CC) $(FLAGS) -c e1_producer.c $(LIBS)
e1_consumer: e1_consumer.o random_num.o
$(CC) $(FLAGS) -o consumer e1_consumer.o random_num.o $(LIBS)
e1_consumer.o: e1_consumer.c
$(CC) $(FLAGS) -c e1_consumer.c $(LIBS)
clean:
rm producer consumer *.o
Output after two consecutive "make" in the command line
$ make
$ gcc -Wall -g -c e1_producer.c -lrt -lpthread
$ gcc -Wall -g -c random_num.c
$ gcc -Wall -g -o producer e1_producer.o random_num.o -lrt -lpthread
$ gcc -Wall -g -c e1_consumer.c -lrt -lpthread
$ gcc -Wall -g -o consumer e1_consumer.o random_num.o -lrt -lpthread
$ make
gcc -Wall -g -o producer e1_producer.o random_num.o -lrt -lpthread
gcc -Wall -g -o consumer e1_consumer.o random_num.o -lrt -lpthread
Why is this happening? When I do the same with another single program the second $ make returns me "nothing to do, bla bla is up to date"

Cflags in Makefile not appearing

I have a makefile, but it seems like the cflags are only working for certain files in my program, and I am not sure why.
Here is what happens when I use make:
$ make
gcc -Wall -ansi -pedantic -g -c main.c
gcc -c fw.c
gcc -c trie.c
gcc -Wall -ansi -pedantic -g -c linked.c
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
You can see that when trying to make fw.c and trie.c it doesn't include the flags, but it does include the flags for the other files.
Here is my makefile:
CC = gcc
CFLAGS = -Wall -ansi -pedantic -g
MAIN = main
OBJS = main.o fw.o trie.o linked.o
all : $(MAIN)
$(MAIN) : $(OBJS) fw.h trie.h linked.h
$(CC) $(CFLAGS) -o fw $(OBJS)
main.o : main.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c main.c
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
linked.o : linked.c trie.h linked.h
$(CC) $(CFLAGS) -c linked.c
rm :
rm *.o $(MAIN) core
I also have an additional problem in that whenever I use make with unchanged files from the last make, it still executes this line:
$ make
gcc -Wall -ansi -pedantic -g -o fw main.o fw.o trie.o linked.o
Whereas usually, it gives me the message "nothing to be done for all". I have tried to compare this makefile to my other working makefiles, but I can't find the error(s). Where have I gone wrong?
You have typos in your Makefile:
fw.o : fw.c fw.h trie.h
$(CC) $(CGLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CGLAGS) -c trie.c
Note the G. Instead, use this:
fw.o : fw.c fw.h trie.h
$(CC) $(CFLAGS) -c fw.c
trie.o : trie.c fw.h trie.h linked.h
$(CC) $(CFLAGS) -c trie.c

how to write a simple makefile for c

I need to write a simple make file for my.c, and so after
make
then my program can be run by
./my
my.c can be compiled by this:
gcc cJ/cJ.c my.c -lcrypto -o my -lm
Thanks
I put this in my makefile
all:my
my: cJ.o my.o
gcc cJ.o -lcrypt my.o -o my
cJ.o: cJ/cJ.c
gcc -c cJ/cJ.c
my.o: my.c
gcc -c my.c -lm
help please
Well, makefiles are just kind of special scripts. Every is unique, for such simple task this would be sufficient:
Makefile:
CC=gcc
CFLAGS=-lm -lcrypto
SOURCES=my.c cJ/cJ.c
all: my
my: $(SOURCES)
$(CC) -o my $(SOURCES) $(CFLAGS)
Later you may want to use some other options such as wildcards %.c to compile in multiple files without having to write them in.
Alternatively:
CC=gcc
CFLAGS=-lm -lcrypto
MY_SOURCES = my.c cJ/cJ.c
MY_OBJS = $(patsubst %.c,%.o, $(MY_SOURCES))
all: my
%o: %.c
$(CC) $(CFLAGS) -c $<
my: $(MY_OBJS)
$(CC) $(CFLAGS) $^ -o $#
Note that lines following each target ("my:", ...) must start with tab (\t), not spaces.
Just a minor correction: put the -lm to the linking step, and there after all object files.
all: my
my: cJ.o my.o
gcc cJ.o my.o -o my -lcrypt -lm
cJ.o: cJ/cJ.c
gcc -c cJ/cJ.c
my.o: my.c
gcc -c my.c
And then, you could work more with automatic variables:
all: my
my: cJ.o my.o
gcc $^ -o $# -lcrypt -lm
cJ.o: cJ/cJ.c
gcc -c $^
my.o: my.c
gcc -c $^
where $# is the target of the current rule and $^ are the prerequisites.
See also http://www.gnu.org/software/make/manual/make.html.
simple make file for your program is
build :
gcc /your_full_path_to_c_file/cJ.c my.c -lcrypto -o my -lm
just copy this in one file keep name of that file as makefile
then run as make build

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