I wrote the following makefile:
CC = gcc
OBJS = Car.o Guide.o GuideSystem.o
DEBUG_OBJS = Car_debug.o Guide_debug.o GuideSystem_debug.o
SOURCE = Car.c Guide.c GuideSystem.c
HEADER = Car.h Guide.h GuideSystem.h list.h set.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror
LIBM = -L. -lib
EXEC = test.exe test1.exe test2.exe test2_debug.exe
TEST_O = test1.o test2.o test2_debug.o test.o
#make test1.exe
test1.exe : $(OBJS) test1.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test1.o $(LIBM) -o $#
#make test2.exe
test2.exe : $(OBJS) test2.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test2.o $(LIBM) -o $#
#make test2_debug.exe
test2_debug.exe : $(OBJS) test2_debug.o
$(CC) $(CFLAGS) -g $(OBJS) test2_debug.o $(LIBM) -o $#
#make test.exe
test.exe : $(OBJS) test.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test.o $(LIBM) -o $#
#Testing (no asserts)
test.o : test.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test1.o : test1.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test2.o : test2.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Guide.o : Guide.c Guide.h list.h Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
GuideSystem.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Car.o : Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
#Debug testing
test2_debug.o : test2.c Guide.h GuideSystem.h
$(CC) -c -g $(CFLAGS) test2.c -o $#
Guide_debug.o : Guide.c Guide.h list.h Car.h
$(CC) -c -g $(CFLAGS) Guide.c -o $#
GuideSystem_debug.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -g $(CFLAGS) GuideSystem.c -o $#
Car_debug.o : Car.h
$(CC) -c -g $(CFLAGS) Car.c -o $#
#Clean builds
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(TEST_O)
When I run make test I get:
gcc test.o -o test
test.o: In function `main':
test.c:(.text+0x29): undefined reference to `createGuide'
... more undefined functions
I have some problem with the makefile but I can't seem to find the problem. All of the other make options work properly, only make test fails.
As I understand it should run:
gcc -c -DNDEBUG -std=c99 -Wall -Werror -pedantic-errors test.c
gcc -o test.exe -DNDEBUG Guide.o GuideSystem.o Car.o test.o -L. -lib
What could be the problem? How can I solve it? Do I have a problem with my makefile?
You didn't define any test target, so make guessed wrongly that you wanted to make a program named test just from test.o (implicit rule).
What you should probably insert in Makefile is:
test: test.exe test2.exe
./test.exe
./test2.exe
.PHONY: test
Related
I have the following makefile
CC=cc
CFLAGS= -Wall -Wextra -pedantic -lm
DEPS = fileMake.h
OBJ = fileMake.o fileFunction.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
fileMake: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
It produces the follwing output:
cc -Wall -Wextra -pedantic -lm secondDegreeFormula.c -o secondDegreeFormula
I would like to move the -lm to the end and remove the extra spaces, like:
cc -Wall -Wextra -pedantic secondDegreeFormula.c -o secondDegreeFormula -lm
how can I do this?
EDIT:
CC=cc
CFLAGS=-Wall -Wextra -pedantic
LIBS=-lm
DEPS=fileMake.h
OBJ=fileMake.o fileFunction.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS) $(LIBS)
fileMake: $(OBJ)
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
EDIT 2:
CC=cc
CFLAGS= -Wall -Wextra -pedantic
LIBS= -lm
DEPS=fileMake.h
OBJ=fileMake.o fileFunction.o
fileMake: $(OBJ)
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
You need to make the dynamic libraries a separate variable and include that where appropriate.
CFLAGS= -Wall -Wextra -pedantic
LIBS= -lm
...
fileMake: $(OBJ)
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
I'm trying to understand if I have create the Makefile right. I have the following files:
Student.h Student.C University.h University.c list.h IDCard.h IDCard.c union.h
Also I have a library mylib which I use the list.h and union.h from.
Furthermore, I have the following hierarchy:
- University
- Student
- list
- IDCard
- union
This means that University imports Student and union and Student import list and IDCard.
The steps I need to follow:
Use the make command to create testing1.exe - release mode without asserts. This file is the runnable of the given testing1.c.
Use make testing2.exe for creating test2.exe - release mode without asserts. This file is the runable of testing2.c.
Use make testing2_debug.exe for creating testing2_debug.exe - debug mode, with asserts. This file is the runable of test2.c.
Use make test for creating test.exe - release mode without asserts. This file is runnable of test.c.
Use make clean to clean so the rebuild will succeed.
The Makefile I wrote looks like:
CC = gcc
OBJS = IDCard.o Student.o University.o
DEBUG_OBJS = IDCard_debug.o Student_debug.o University_debug.o
SOURCE = IDCard.c Student.c University.c
HEADER = IDCard.h Student.h University.h list.h union.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror -DNDEBUG -L. -mylib
EXEC = testing.exe testing1.exe testing2.exe testing2_debug.exe
testing_O = testing1.o testing2.o testing2_debug.o testing.o
#make testing1.exe
testing1.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing2.exe
testing2.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#testing2_debug.exe
testing2_debug.exe : $(DEBUG_OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing.exe
testing.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
testing1.o : testing1.c Student.h University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
Student.o : list.h IDCard.h Student.c Student.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
University.o : union.h University.c University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
testing2_debug.o : testing2.c Student.h University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
Student_debug.o : list.h IDCard.h Student.c Student.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
University_debug.o : union.h University.c University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
IDCard_debug.o : IDCard.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(testing_O)
I'm a bit new to creating Makefiles so I'm try to make as few mistakes as possible. Does my Makefile do what I need? Can it be simplified? Does it follow the conventions?
$*.o shouldn't be a dependency. $(OBJS) already covers that.
As a general rule, you can avoid targets for individual object files.
Here's an example target that may need modification to suit your needs:
%.o: %.c %.h
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c %.h
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
This requires the header file to have the same base name as the source file.
Another option that may work is listing off the header file dependencies of each object file and then doing the matching:
testing1.o: Student.h University.h
Student.o: list.h IDCard.h Student.h
University.o: union.h University.h
IDCard.o: IDCard.h
testing2_debug.o: Student.h University.h
Student_debug.o: list.h IDCard.h Student.h
University_debug.o: union.h University.h
IDCard_debug.o: IDCard.h
%.o: %.c
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
A similar rule can be followed for .exe files:
%.exe: $(OBJS)
<tab>$(CC) -DNDEBUG $(CFLAGS) $^ -o $# -L. -lmylib
%_debug.exe: $(DEBUG_OBJS)
<tab>$(CC) -g $(CFLAGS) $^ -o $# -L. -lmylib
Also, make sure to replace <tab> in these examples with hard tabs for your Makefile to be valid.
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
but .h files aren't compiled
As a general style form list .c dependencies before .h dependencies.
EDIT: Community Wiki. If it weren't for the clarifying comment by OP I would now delete this post.
I'm trying to change my makefile to redirect the .o to a lib folder (and have the .c in a src folder). I would also like the executables to be at the same level as the makefile.
As for the .h, I have no idea where to put it!
CC = gcc
CFLAGS = -std=c11 -Wpedantic -Wall -Wextra -Wconversion -Werror -fPIC -pthread -D_XOPEN_SOURCE=500 -fstack-protector
LDLIBS = -lrt
RM = rm -f
ARFLAGS = rs
all: server client info_proc info_user
server: server.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
server.o: server.c header.h
gcc -c server.c
client: client.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
client.o: client.c header.h
header.o: header.c header.h
gcc -c header.c
info_proc: info_proc.o
info_proc.o: info_proc.c
gcc -c info_proc.c
info_user: info_user.o
info_user.o: info_user.c
gcc -c info_user.c
rmpipe:
$(RM) question_pipe
clean:
$(RM) server client info_proc info_user question_pipe *.o *~$
You could do something like this:
all: main
main: lib/a.o lib/b.o lib/main.o
$(CC) $(CFLAGS) -o $# $^
lib/a.o: a.c
$(CC) $(CFLAGS) -c -o $# $<
lib/b.o: b.c
$(CC) $(CFLAGS) -c -o $# $<
lib/main.o: main.c
$(CC) $(CFLAGS) -c -o $# $<
Or instead of writing your own Makefile you could use one of these build
tools:
GNU Autotools
Cmake
SCons
which on the long run are much easier to maintain than a self-written
Makefile.
This question already has answers here:
Wildcard targets in a Makefile
(3 answers)
Closed 9 years ago.
This is what my current version looks like:
CC = gcc
CFLAGS = `sdl-config --cflags`
LIBS = `sdl-config --libs` -lSDL_ttf
program: uprising
uprising: main.o init.o display.o move.o global.o control.o battle.o
$(CC) main.o init.o display.o move.o global.o control.o battle.o -o uprising $(CFLAGS) $(LIBS)
global.o: global.c
$(CC) -c global.c -o global.o $(CFLAGS)
battle.o: battle.c
$(CC) -c battle.c -o battle.o $(CFLAGS)
main.o: main.c
$(CC) -c main.c -o main.o $(CFLAGS)
init.o: init.c
$(CC) -c init.c -o init.o $(CFLAGS)
display.o: display.c
$(CC) -c display.c -o display.o $(CFLAGS)
move.o: move.c
$(CC) -c move.c -o move.o $(CFLAGS)
control.o: control.c
$(CC) -c control.c -o control.o $(CFLAGS)
clean:
rm -f *~ *# uprising init.o main.o display.o move.o global.o control.o
You see, every module gets compiled in the same manner. I've been tired of editing this makefile when adding a new module to my project. Is there any way to type a module's name for just once (as if it was a argument), and let makefile build each module in the same way?
If you change LIBS to LDLIBS, you can write the entire makefile in just this:
CC = gcc
CFLAGS = `sdl-config --cflags`
LDLIBS = `sdl-config --libs` -lSDL_ttf
program: uprising
uprising: main.o init.o display.o move.o global.o control.o battle.o
$(CC) $^ -o $# $(CFLAGS) $(LDLIBS)
clean:
rm -f *~ *# uprising *.o
My makefile is compiling write_time.o although i'm not giving it any rule. However, when I actually write a rule for it, it wouldn't compile. Any suggestion on what might cause this problem? Below is my makefile:
INCLUDES = -I../include -I/opt/local/include
CC = gcc
OBJS = image_io.o xcorr.o textfile_io.o main.o array_processing.o \
fit2d.o poly.o mattran.o matsolve.o nelder_mead.o process.o \
open_seq_file.o write_time.o close_seq_file.o
DEBUGS = -g
CFLAGS = $(INCLUDES) -Wall -O2 $(DEBUGS)
DESTDIR = ../bin
LDFLAGS = -L. -L/opt/local/lib -ltiff -lm -L../lib -lmatrix ../include/seq_io.h
DEPS = ../include/file_io.h ../include/corr.h \
../include/matrix.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h ../include/seq_io.h
#../include/nmsimplex.h
all: $(DESTDIR)/main
image_io.o: image_io.c ../include/file_io.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h
$(CC) $(CFLAGS) -o $# -c $<
xcorr.o: xcorr.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
textfile_io.o: textfile_io.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
array_processing.o: array_processing.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
fit2d.o: fit2d.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
poly.o: poly.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
nelder_mead.o: nelder_mead.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
# nmsimplex.o: nmsimplex.c ../include/nmsimplex.h
# $(CC) $(CFLAGS) -o $# -c $<
process.o: process.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
mattran.o: mattran.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
matsolve.o: matsolve.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
open_seq_file.o: open_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
close_seq_file.o: close_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
main.o: main.c ../include/file_io.h ../include/nmsimplex.h ../include/corr.h ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -fopenmp -c $<
$(DESTDIR)/main: $(OBJS)
$(CC) -o $# -fopenmp $^ $(LDFLAGS)
.PHONY: clean
clean:
rm -f *.o *~
This compiles fine. But when I add in:
write_time.o: write_time.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
I get the error:
make: *** No rule to make target `../include/seq_io.h', needed by `write_time.o'. Stop.
That error probably means that ../include/seq_io.h doesn't exist. You've listed it as a dependency, and make insists that dependencies either exist or that there is some way to automatically create them.