My makefile is compiling write_time.o although i'm not giving it any rule. However, when I actually write a rule for it, it wouldn't compile. Any suggestion on what might cause this problem? Below is my makefile:
INCLUDES = -I../include -I/opt/local/include
CC = gcc
OBJS = image_io.o xcorr.o textfile_io.o main.o array_processing.o \
fit2d.o poly.o mattran.o matsolve.o nelder_mead.o process.o \
open_seq_file.o write_time.o close_seq_file.o
DEBUGS = -g
CFLAGS = $(INCLUDES) -Wall -O2 $(DEBUGS)
DESTDIR = ../bin
LDFLAGS = -L. -L/opt/local/lib -ltiff -lm -L../lib -lmatrix ../include/seq_io.h
DEPS = ../include/file_io.h ../include/corr.h \
../include/matrix.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h ../include/seq_io.h
#../include/nmsimplex.h
all: $(DESTDIR)/main
image_io.o: image_io.c ../include/file_io.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h
$(CC) $(CFLAGS) -o $# -c $<
xcorr.o: xcorr.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
textfile_io.o: textfile_io.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
array_processing.o: array_processing.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
fit2d.o: fit2d.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
poly.o: poly.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
nelder_mead.o: nelder_mead.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
# nmsimplex.o: nmsimplex.c ../include/nmsimplex.h
# $(CC) $(CFLAGS) -o $# -c $<
process.o: process.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
mattran.o: mattran.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
matsolve.o: matsolve.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
open_seq_file.o: open_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
close_seq_file.o: close_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
main.o: main.c ../include/file_io.h ../include/nmsimplex.h ../include/corr.h ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -fopenmp -c $<
$(DESTDIR)/main: $(OBJS)
$(CC) -o $# -fopenmp $^ $(LDFLAGS)
.PHONY: clean
clean:
rm -f *.o *~
This compiles fine. But when I add in:
write_time.o: write_time.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
I get the error:
make: *** No rule to make target `../include/seq_io.h', needed by `write_time.o'. Stop.
That error probably means that ../include/seq_io.h doesn't exist. You've listed it as a dependency, and make insists that dependencies either exist or that there is some way to automatically create them.
Related
I have the following makefile
CC=cc
CFLAGS= -Wall -Wextra -pedantic -lm
DEPS = fileMake.h
OBJ = fileMake.o fileFunction.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
fileMake: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
It produces the follwing output:
cc -Wall -Wextra -pedantic -lm secondDegreeFormula.c -o secondDegreeFormula
I would like to move the -lm to the end and remove the extra spaces, like:
cc -Wall -Wextra -pedantic secondDegreeFormula.c -o secondDegreeFormula -lm
how can I do this?
EDIT:
CC=cc
CFLAGS=-Wall -Wextra -pedantic
LIBS=-lm
DEPS=fileMake.h
OBJ=fileMake.o fileFunction.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS) $(LIBS)
fileMake: $(OBJ)
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
EDIT 2:
CC=cc
CFLAGS= -Wall -Wextra -pedantic
LIBS= -lm
DEPS=fileMake.h
OBJ=fileMake.o fileFunction.o
fileMake: $(OBJ)
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
You need to make the dynamic libraries a separate variable and include that where appropriate.
CFLAGS= -Wall -Wextra -pedantic
LIBS= -lm
...
fileMake: $(OBJ)
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
I wrote the following makefile:
CC = gcc
OBJS = Car.o Guide.o GuideSystem.o
DEBUG_OBJS = Car_debug.o Guide_debug.o GuideSystem_debug.o
SOURCE = Car.c Guide.c GuideSystem.c
HEADER = Car.h Guide.h GuideSystem.h list.h set.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror
LIBM = -L. -lib
EXEC = test.exe test1.exe test2.exe test2_debug.exe
TEST_O = test1.o test2.o test2_debug.o test.o
#make test1.exe
test1.exe : $(OBJS) test1.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test1.o $(LIBM) -o $#
#make test2.exe
test2.exe : $(OBJS) test2.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test2.o $(LIBM) -o $#
#make test2_debug.exe
test2_debug.exe : $(OBJS) test2_debug.o
$(CC) $(CFLAGS) -g $(OBJS) test2_debug.o $(LIBM) -o $#
#make test.exe
test.exe : $(OBJS) test.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test.o $(LIBM) -o $#
#Testing (no asserts)
test.o : test.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test1.o : test1.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test2.o : test2.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Guide.o : Guide.c Guide.h list.h Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
GuideSystem.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Car.o : Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
#Debug testing
test2_debug.o : test2.c Guide.h GuideSystem.h
$(CC) -c -g $(CFLAGS) test2.c -o $#
Guide_debug.o : Guide.c Guide.h list.h Car.h
$(CC) -c -g $(CFLAGS) Guide.c -o $#
GuideSystem_debug.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -g $(CFLAGS) GuideSystem.c -o $#
Car_debug.o : Car.h
$(CC) -c -g $(CFLAGS) Car.c -o $#
#Clean builds
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(TEST_O)
When I run make test I get:
gcc test.o -o test
test.o: In function `main':
test.c:(.text+0x29): undefined reference to `createGuide'
... more undefined functions
I have some problem with the makefile but I can't seem to find the problem. All of the other make options work properly, only make test fails.
As I understand it should run:
gcc -c -DNDEBUG -std=c99 -Wall -Werror -pedantic-errors test.c
gcc -o test.exe -DNDEBUG Guide.o GuideSystem.o Car.o test.o -L. -lib
What could be the problem? How can I solve it? Do I have a problem with my makefile?
You didn't define any test target, so make guessed wrongly that you wanted to make a program named test just from test.o (implicit rule).
What you should probably insert in Makefile is:
test: test.exe test2.exe
./test.exe
./test2.exe
.PHONY: test
CC=gcc
CFLAGS=-Wall -g -std=c11 -c
LDFLAGS = -shared
BIN = ./bin/
SRC = ./src/
SRC1 = ./src/test1.c
SRC2 = ./src/test2.c
SRC_FILES = $(wildcard ./src/*.c)
program:
$(CC) $(CFLAGS) $(LDFLAGS) $(SRC1) -Iinclude -o $(BIN)test1.so
$(CC) $(CFLAGS) $(LDFLAGS) $(SRC2) -Iinclude -o $(BIN)test2.so
test1:
$(CC) $(CFLAGS) $(LDFLAGS) $(SRC1) -Iinclude -o $(BIN)test2.so
test2:
$(CC) $(CFLAGS) $(LDFLAGS) $(SRC2) -Iinclude -o $(BIN)test2.so
cls:
clear
clean:
rm ./bin/*
so my folder set up is the root which is called temp, then inside that another folder called compile, within that is the the makefile, src, include, bin. what i need help doing is having the .so file output to temp instead of to bin but im not sure how to do that
Just use the same technique that you used with BIN.
$(CC) $(CFLAGS) $(LDFLAGS) $(SRC2) -Iinclude -o ../test2.so
I have a makefile which does what I want with the compilation but I want it also to make a library instead of only object files.
CC=gcc
CFLAGS=-g -Wall
DEPS = tree.h
OBJ = main.o tree.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
tree: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
clean:
rm -f *.o tree
Now I want the makefile to be something like this:
gcc -Wall -g -c tree.c
ar -r libtree.a tree.o
gcc main.c -o main -ltree -L.
./main
What I have to add to my existing makefile?
This should do what you want:
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
lib%.a: %.o
ar -r $# $^
main: $(OBJ) $(DEPS:%.h=lib%.a)
$(CC) -o $# $^ $(CFLAGS) $(DEPS:%.h=-l%) -L.
Note that this only works in GNU Make (in particular, the % in $(DEPS:%.h=lib%.a) is a GNU-specific extension).
I'm trying to build project. There are two directories:
A/
foo.c
foo.h
B/
main.c
Makefile
main.c includes "foo.h". What do i have to write in Makefile to build the project.
I did this
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
foo.o: foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o
It cant find foo.c
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o $(INCLUDE_DIR)/foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
$(INCLUDE_DIR)/foo.o: $(INCLUDE_DIR)/foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o $(INCLUDE_DIR)/*.o
You need to tell make the relative path to the files.
IIRC you can use
foo.o: ../A/foo.c
$(CC) $(CFLAGS) $< -c $%
but I guess that's not really a solution?