I'm trying to build project. There are two directories:
A/
foo.c
foo.h
B/
main.c
Makefile
main.c includes "foo.h". What do i have to write in Makefile to build the project.
I did this
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
foo.o: foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o
It cant find foo.c
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o $(INCLUDE_DIR)/foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
$(INCLUDE_DIR)/foo.o: $(INCLUDE_DIR)/foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o $(INCLUDE_DIR)/*.o
You need to tell make the relative path to the files.
IIRC you can use
foo.o: ../A/foo.c
$(CC) $(CFLAGS) $< -c $%
but I guess that's not really a solution?
Related
I'm trying to understand if I have create the Makefile right. I have the following files:
Student.h Student.C University.h University.c list.h IDCard.h IDCard.c union.h
Also I have a library mylib which I use the list.h and union.h from.
Furthermore, I have the following hierarchy:
- University
- Student
- list
- IDCard
- union
This means that University imports Student and union and Student import list and IDCard.
The steps I need to follow:
Use the make command to create testing1.exe - release mode without asserts. This file is the runnable of the given testing1.c.
Use make testing2.exe for creating test2.exe - release mode without asserts. This file is the runable of testing2.c.
Use make testing2_debug.exe for creating testing2_debug.exe - debug mode, with asserts. This file is the runable of test2.c.
Use make test for creating test.exe - release mode without asserts. This file is runnable of test.c.
Use make clean to clean so the rebuild will succeed.
The Makefile I wrote looks like:
CC = gcc
OBJS = IDCard.o Student.o University.o
DEBUG_OBJS = IDCard_debug.o Student_debug.o University_debug.o
SOURCE = IDCard.c Student.c University.c
HEADER = IDCard.h Student.h University.h list.h union.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror -DNDEBUG -L. -mylib
EXEC = testing.exe testing1.exe testing2.exe testing2_debug.exe
testing_O = testing1.o testing2.o testing2_debug.o testing.o
#make testing1.exe
testing1.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing2.exe
testing2.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#testing2_debug.exe
testing2_debug.exe : $(DEBUG_OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing.exe
testing.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
testing1.o : testing1.c Student.h University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
Student.o : list.h IDCard.h Student.c Student.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
University.o : union.h University.c University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
testing2_debug.o : testing2.c Student.h University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
Student_debug.o : list.h IDCard.h Student.c Student.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
University_debug.o : union.h University.c University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
IDCard_debug.o : IDCard.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(testing_O)
I'm a bit new to creating Makefiles so I'm try to make as few mistakes as possible. Does my Makefile do what I need? Can it be simplified? Does it follow the conventions?
$*.o shouldn't be a dependency. $(OBJS) already covers that.
As a general rule, you can avoid targets for individual object files.
Here's an example target that may need modification to suit your needs:
%.o: %.c %.h
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c %.h
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
This requires the header file to have the same base name as the source file.
Another option that may work is listing off the header file dependencies of each object file and then doing the matching:
testing1.o: Student.h University.h
Student.o: list.h IDCard.h Student.h
University.o: union.h University.h
IDCard.o: IDCard.h
testing2_debug.o: Student.h University.h
Student_debug.o: list.h IDCard.h Student.h
University_debug.o: union.h University.h
IDCard_debug.o: IDCard.h
%.o: %.c
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
A similar rule can be followed for .exe files:
%.exe: $(OBJS)
<tab>$(CC) -DNDEBUG $(CFLAGS) $^ -o $# -L. -lmylib
%_debug.exe: $(DEBUG_OBJS)
<tab>$(CC) -g $(CFLAGS) $^ -o $# -L. -lmylib
Also, make sure to replace <tab> in these examples with hard tabs for your Makefile to be valid.
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
but .h files aren't compiled
As a general style form list .c dependencies before .h dependencies.
EDIT: Community Wiki. If it weren't for the clarifying comment by OP I would now delete this post.
I'm trying to change my makefile to redirect the .o to a lib folder (and have the .c in a src folder). I would also like the executables to be at the same level as the makefile.
As for the .h, I have no idea where to put it!
CC = gcc
CFLAGS = -std=c11 -Wpedantic -Wall -Wextra -Wconversion -Werror -fPIC -pthread -D_XOPEN_SOURCE=500 -fstack-protector
LDLIBS = -lrt
RM = rm -f
ARFLAGS = rs
all: server client info_proc info_user
server: server.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
server.o: server.c header.h
gcc -c server.c
client: client.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
client.o: client.c header.h
header.o: header.c header.h
gcc -c header.c
info_proc: info_proc.o
info_proc.o: info_proc.c
gcc -c info_proc.c
info_user: info_user.o
info_user.o: info_user.c
gcc -c info_user.c
rmpipe:
$(RM) question_pipe
clean:
$(RM) server client info_proc info_user question_pipe *.o *~$
You could do something like this:
all: main
main: lib/a.o lib/b.o lib/main.o
$(CC) $(CFLAGS) -o $# $^
lib/a.o: a.c
$(CC) $(CFLAGS) -c -o $# $<
lib/b.o: b.c
$(CC) $(CFLAGS) -c -o $# $<
lib/main.o: main.c
$(CC) $(CFLAGS) -c -o $# $<
Or instead of writing your own Makefile you could use one of these build
tools:
GNU Autotools
Cmake
SCons
which on the long run are much easier to maintain than a self-written
Makefile.
My makefile is compiling write_time.o although i'm not giving it any rule. However, when I actually write a rule for it, it wouldn't compile. Any suggestion on what might cause this problem? Below is my makefile:
INCLUDES = -I../include -I/opt/local/include
CC = gcc
OBJS = image_io.o xcorr.o textfile_io.o main.o array_processing.o \
fit2d.o poly.o mattran.o matsolve.o nelder_mead.o process.o \
open_seq_file.o write_time.o close_seq_file.o
DEBUGS = -g
CFLAGS = $(INCLUDES) -Wall -O2 $(DEBUGS)
DESTDIR = ../bin
LDFLAGS = -L. -L/opt/local/lib -ltiff -lm -L../lib -lmatrix ../include/seq_io.h
DEPS = ../include/file_io.h ../include/corr.h \
../include/matrix.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h ../include/seq_io.h
#../include/nmsimplex.h
all: $(DESTDIR)/main
image_io.o: image_io.c ../include/file_io.h /opt/local/include/tiffio.h \
/opt/local/include/tiff.h
$(CC) $(CFLAGS) -o $# -c $<
xcorr.o: xcorr.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
textfile_io.o: textfile_io.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
array_processing.o: array_processing.c ../include/file_io.h
$(CC) $(CFLAGS) -o $# -c $<
fit2d.o: fit2d.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
poly.o: poly.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
nelder_mead.o: nelder_mead.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
# nmsimplex.o: nmsimplex.c ../include/nmsimplex.h
# $(CC) $(CFLAGS) -o $# -c $<
process.o: process.c ../include/corr.h
$(CC) $(CFLAGS) -o $# -c $<
mattran.o: mattran.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
matsolve.o: matsolve.c ../include/matrix.h
$(CC) $(CFLAGS) -o $# -c $<
open_seq_file.o: open_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
close_seq_file.o: close_seq_file.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
main.o: main.c ../include/file_io.h ../include/nmsimplex.h ../include/corr.h ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -fopenmp -c $<
$(DESTDIR)/main: $(OBJS)
$(CC) -o $# -fopenmp $^ $(LDFLAGS)
.PHONY: clean
clean:
rm -f *.o *~
This compiles fine. But when I add in:
write_time.o: write_time.c ../include/seq_io.h
$(CC) $(CFLAGS) -o $# -c $<
I get the error:
make: *** No rule to make target `../include/seq_io.h', needed by `write_time.o'. Stop.
That error probably means that ../include/seq_io.h doesn't exist. You've listed it as a dependency, and make insists that dependencies either exist or that there is some way to automatically create them.
I need to modify the Makefile I have to store only the object file associated with "record.c" into the bin folder. Here is what my directory structure looks like before executing Make.
bin/
include/
-hash_table.h
-history.h
-parser.h
-record.h
-shell.h
-variables.h
lib/
obj/
src/
-hash_table.c
-history.c
-parser.c
-record.c
-shutil.c
-sshell.c
-variables.c
...and here is the Makefile:
# Beginning of Makefile
SRC = src/shutil.c src/parser.c src/sshell.c src/history.c src/hash_table.c src/variables.c src/record.c
OBJS = obj/shutil.o obj/parser.o obj/sshell.o obj/history.o obj/hash_table.o obj/variables.o bin/record.o //<----
HEADER_FILES = include/shell.h include/parser.h include/history.h include/hash_table.h include/variables.h include/record.h
EXECUTABLE = sshell
LIBS = lib/libshell.so lib/libparser.so lib/libhistory.so lib/libhash_table.so lib/libvariables.so lib/librecord.so
LIBCFLAGS = $(CFLAGS) -D_REENTRANT -fPIC
CFLAGS = -Wall
CC = gcc
# End of configuration options
#What needs to be built to make all files and dependencies
all: $(EXECUTABLE)
#Create the main executable
$(EXECUTABLE): $(OBJS) $(LIBS)
$(CC) -o $(EXECUTABLE) obj/sshell.o -Llib -lparser -lshell -lhistory -lhash_table -lvariables -lrecord
#Create the library files
lib/libparser.so: obj/parser.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libshell.so: obj/shutil.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libhistory.so: obj/history.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libhash_table.so: obj/hash_table.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libvariables.so: obj/variables.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/librecord.so: bin/record.o //<----
$(CC) $(LIBFLAGS) -shared $^ -o $#
#Recursively build object files
obj/%.o: src/%.c //<---- I feel like this is causing the problem.
$(CC) $(CFLAGS) -I./include/ -c $< -o $#
#Define dependencies for objects based on header files
#We are overly conservative here, parser.o should depend on parser.h only
$(OBJS) : $(HEADER_FILES)
clean:
-rm -f $(EXECUTABLE) obj/*.o lib/*.so lib/*.a bin/*.o
-rm -f .sshell_history.txt
run: $(EXECUTABLE)
(export LD_LIBRARY_PATH=lib; ./$(EXECUTABLE))
# End of Makefile
With what I have done (most likely completely off) it doesn't compile record.c and says bin/record.o does not exist. I am not really experienced with Makefiles so I am wondering if I can have some help. Thanks!
Try using the rule .c.o instead of obj/%.o: src/%.c
Edit:
If that doesn't work, maybe adding the following rule will do the job:
bin/%.o: src/%.c
$(CC) $(CFLAGS) -I./include/ -c $< -o $#
I have a makefile which does what I want with the compilation but I want it also to make a library instead of only object files.
CC=gcc
CFLAGS=-g -Wall
DEPS = tree.h
OBJ = main.o tree.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
tree: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
clean:
rm -f *.o tree
Now I want the makefile to be something like this:
gcc -Wall -g -c tree.c
ar -r libtree.a tree.o
gcc main.c -o main -ltree -L.
./main
What I have to add to my existing makefile?
This should do what you want:
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
lib%.a: %.o
ar -r $# $^
main: $(OBJ) $(DEPS:%.h=lib%.a)
$(CC) -o $# $^ $(CFLAGS) $(DEPS:%.h=-l%) -L.
Note that this only works in GNU Make (in particular, the % in $(DEPS:%.h=lib%.a) is a GNU-specific extension).