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Wildcard targets in a Makefile
(3 answers)
Closed 9 years ago.
This is what my current version looks like:
CC = gcc
CFLAGS = `sdl-config --cflags`
LIBS = `sdl-config --libs` -lSDL_ttf
program: uprising
uprising: main.o init.o display.o move.o global.o control.o battle.o
$(CC) main.o init.o display.o move.o global.o control.o battle.o -o uprising $(CFLAGS) $(LIBS)
global.o: global.c
$(CC) -c global.c -o global.o $(CFLAGS)
battle.o: battle.c
$(CC) -c battle.c -o battle.o $(CFLAGS)
main.o: main.c
$(CC) -c main.c -o main.o $(CFLAGS)
init.o: init.c
$(CC) -c init.c -o init.o $(CFLAGS)
display.o: display.c
$(CC) -c display.c -o display.o $(CFLAGS)
move.o: move.c
$(CC) -c move.c -o move.o $(CFLAGS)
control.o: control.c
$(CC) -c control.c -o control.o $(CFLAGS)
clean:
rm -f *~ *# uprising init.o main.o display.o move.o global.o control.o
You see, every module gets compiled in the same manner. I've been tired of editing this makefile when adding a new module to my project. Is there any way to type a module's name for just once (as if it was a argument), and let makefile build each module in the same way?
If you change LIBS to LDLIBS, you can write the entire makefile in just this:
CC = gcc
CFLAGS = `sdl-config --cflags`
LDLIBS = `sdl-config --libs` -lSDL_ttf
program: uprising
uprising: main.o init.o display.o move.o global.o control.o battle.o
$(CC) $^ -o $# $(CFLAGS) $(LDLIBS)
clean:
rm -f *~ *# uprising *.o
Related
I wrote the following makefile:
CC = gcc
OBJS = Car.o Guide.o GuideSystem.o
DEBUG_OBJS = Car_debug.o Guide_debug.o GuideSystem_debug.o
SOURCE = Car.c Guide.c GuideSystem.c
HEADER = Car.h Guide.h GuideSystem.h list.h set.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror
LIBM = -L. -lib
EXEC = test.exe test1.exe test2.exe test2_debug.exe
TEST_O = test1.o test2.o test2_debug.o test.o
#make test1.exe
test1.exe : $(OBJS) test1.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test1.o $(LIBM) -o $#
#make test2.exe
test2.exe : $(OBJS) test2.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test2.o $(LIBM) -o $#
#make test2_debug.exe
test2_debug.exe : $(OBJS) test2_debug.o
$(CC) $(CFLAGS) -g $(OBJS) test2_debug.o $(LIBM) -o $#
#make test.exe
test.exe : $(OBJS) test.o
$(CC) $(CFLAGS) -DNDEBUG $(OBJS) test.o $(LIBM) -o $#
#Testing (no asserts)
test.o : test.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test1.o : test1.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
test2.o : test2.c Guide.h GuideSystem.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Guide.o : Guide.c Guide.h list.h Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
GuideSystem.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
Car.o : Car.h
$(CC) -c -DNDEBUG $*.c $(CFLAGS)
#Debug testing
test2_debug.o : test2.c Guide.h GuideSystem.h
$(CC) -c -g $(CFLAGS) test2.c -o $#
Guide_debug.o : Guide.c Guide.h list.h Car.h
$(CC) -c -g $(CFLAGS) Guide.c -o $#
GuideSystem_debug.o : GuideSystem.c GuideSystem.h set.h
$(CC) -c -g $(CFLAGS) GuideSystem.c -o $#
Car_debug.o : Car.h
$(CC) -c -g $(CFLAGS) Car.c -o $#
#Clean builds
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(TEST_O)
When I run make test I get:
gcc test.o -o test
test.o: In function `main':
test.c:(.text+0x29): undefined reference to `createGuide'
... more undefined functions
I have some problem with the makefile but I can't seem to find the problem. All of the other make options work properly, only make test fails.
As I understand it should run:
gcc -c -DNDEBUG -std=c99 -Wall -Werror -pedantic-errors test.c
gcc -o test.exe -DNDEBUG Guide.o GuideSystem.o Car.o test.o -L. -lib
What could be the problem? How can I solve it? Do I have a problem with my makefile?
You didn't define any test target, so make guessed wrongly that you wanted to make a program named test just from test.o (implicit rule).
What you should probably insert in Makefile is:
test: test.exe test2.exe
./test.exe
./test2.exe
.PHONY: test
I'm trying to change my makefile to redirect the .o to a lib folder (and have the .c in a src folder). I would also like the executables to be at the same level as the makefile.
As for the .h, I have no idea where to put it!
CC = gcc
CFLAGS = -std=c11 -Wpedantic -Wall -Wextra -Wconversion -Werror -fPIC -pthread -D_XOPEN_SOURCE=500 -fstack-protector
LDLIBS = -lrt
RM = rm -f
ARFLAGS = rs
all: server client info_proc info_user
server: server.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
server.o: server.c header.h
gcc -c server.c
client: client.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
client.o: client.c header.h
header.o: header.c header.h
gcc -c header.c
info_proc: info_proc.o
info_proc.o: info_proc.c
gcc -c info_proc.c
info_user: info_user.o
info_user.o: info_user.c
gcc -c info_user.c
rmpipe:
$(RM) question_pipe
clean:
$(RM) server client info_proc info_user question_pipe *.o *~$
You could do something like this:
all: main
main: lib/a.o lib/b.o lib/main.o
$(CC) $(CFLAGS) -o $# $^
lib/a.o: a.c
$(CC) $(CFLAGS) -c -o $# $<
lib/b.o: b.c
$(CC) $(CFLAGS) -c -o $# $<
lib/main.o: main.c
$(CC) $(CFLAGS) -c -o $# $<
Or instead of writing your own Makefile you could use one of these build
tools:
GNU Autotools
Cmake
SCons
which on the long run are much easier to maintain than a self-written
Makefile.
Hi i have to write a code where i'll be combining NASM (assembly) with C and allegro library
CC = gcc
OBJ = main.o func.o
BIN = program
CFLAGS = -m32
$(BIN): $(OBJ)
$(CC) $(OBJ) $(CFLAGS) -o $(BIN)
main.o: main.c
$(CC) $(CFLAGS) -c main.c -o main.o
func.o: func.s
nasm -f elf func.s
how do I add allegro-confing --libs here? and where?
Given this makefile, you should add it to the link line:
$(BIN): $(OBJ)
$(CC) $(CFLAGS) -o $(BIN) $(OBJ) `allegro-config --libs`
I have a makefile which does what I want with the compilation but I want it also to make a library instead of only object files.
CC=gcc
CFLAGS=-g -Wall
DEPS = tree.h
OBJ = main.o tree.o
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
tree: $(OBJ)
$(CC) -o $# $^ $(CFLAGS)
clean:
rm -f *.o tree
Now I want the makefile to be something like this:
gcc -Wall -g -c tree.c
ar -r libtree.a tree.o
gcc main.c -o main -ltree -L.
./main
What I have to add to my existing makefile?
This should do what you want:
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
lib%.a: %.o
ar -r $# $^
main: $(OBJ) $(DEPS:%.h=lib%.a)
$(CC) -o $# $^ $(CFLAGS) $(DEPS:%.h=-l%) -L.
Note that this only works in GNU Make (in particular, the % in $(DEPS:%.h=lib%.a) is a GNU-specific extension).
I'm trying to build project. There are two directories:
A/
foo.c
foo.h
B/
main.c
Makefile
main.c includes "foo.h". What do i have to write in Makefile to build the project.
I did this
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
foo.o: foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o
It cant find foo.c
INCLUDE_DIR=../A
LIBS=-lm
CC = gcc
CFLAGS = -c -Wall -I$(INCLUDE_DIR)
default:
#make clean
#make main
sample: main.o $(INCLUDE_DIR)/foo.o
$(CC) $(LIBS) $? -o $#
main.o: main.c
$(CC) $(CFLAGS) $< -c $%
$(INCLUDE_DIR)/foo.o: $(INCLUDE_DIR)/foo.c
$(CC) $(CFLAGS) $< -c $%
clean:
#rm -rf *.o $(INCLUDE_DIR)/*.o
You need to tell make the relative path to the files.
IIRC you can use
foo.o: ../A/foo.c
$(CC) $(CFLAGS) $< -c $%
but I guess that's not really a solution?