Why is my makefile recompiling even if I just compiled the source? - c

Question

I have a simple makefile that compiles a p.c file to an executable using gcc on Linux.
The p.c file depends on a a.h file.
My makefile looks like this:
//makefile
CC = gcc
build: p.c a.h
$(CC) -o out p.c
clean:
rm -f *.exe
rebuild: clean build

Answer 1

Your makefile doesn't produce the files it promises to produce, namely build, clean and rebuild. Since these targets are not files they should be marked as phony targets:
.PHONY: build clean rebuild
build target should be:
build : out
out : p.c a.h
$(CC) -o $# p.c

Answer 2

This part
build: p.c a.h
$(CC) -o out p.c
says "I'm compiling with $(CC) -o out p.c and the result will be a file named 'build'". Since you lied to make (this creates the out file instead), it will try building 'build' again.
There's a lesson for Makefile writers here: always use the $# variable (denoting the target) to avoid this error:
out: p.c a.h
$(CC) -o $# p.c
For more advice, see Paul's Rules for Makefiles.

Answer 3

Learner, here is an example of using a variable to store the name of the executable. This way you only need to specify it in one place at the start of your Makefile:
EXECUTABLE = out
.PHONY: build clean rebuild
build: $(EXECUTABLE)
$(EXECUTABLE): p.c a.h
$(CC) -o $# p.c
clean:
rm -f $(EXECUTABLE)
rebuild: clean build
Normally you would also have your .c and .h files listed in variables too so that you can add/remove files from your build easily without having to search through your Makefile for all of the places that they are used.

Answer 4

Makefiles have the general syntax:
target : dependencies
commands to make target from dependencies
So your Makefile expects to make a file called build using the build : p.c a.h target.
Since the commands don't actually make this file each time you call make it's having to redo the command.
(PS: Linux binaries don't have a .exe extension)

Answer 5

If you want to avoid always recompiling the source, then your target should depend on the object file, not the source file:
target.exe : p.o
$(CC) -o $# $?;
p.o: p.c a.h
$(CC) -c $# $?;
A typical makefile doesn't usually have an explicit rule per object file, nor does it usually list explicit dependencies between implementation and header files; you usually see an implicit rule like
%.o : %.c
$(CC) -c $(CFLAGS) $?;
(where $? indicates the list of prerequisites for that target) or, if your project is dead simple (one source file), you don't even need that; you can usually get away with
all: target
target: target.o
assuming you have a file named target.c, the above will build target using the default compiler and CFLAGS options.
Likewise, a typical makefile (at least in my experience) doesn't explicitly list header dependencies; rather, it relies on a compiler option to generate those dependency lists automagically (for gcc, that option is -M). See here for an example.

Answer 6

I have understood that it is necessary for the 'target' and 'output file' names to match fully for the make to be able to recognize if recompilation is not required. So in case of Windows environment (as make I have tried mingw32-make.exe) it should be like this:
build.exe: p.c a.h
gcc -o build.exe p.c
or
build.exe: p.c a.h
gcc -o build p.c # .exe is added automatically to generated file
This code will lead to recompilation always when make is called:
build: p.c a.h
gcc -o build p.c # target is "build" and it is not the same as "build.exe" which is the output of compilation