I would like to call flex to build a .l file, then call gcc to build everything.
I tryed:
comp:
lex scanner.l \
gcc -o a.out main.c hash.c -I.
error:
lex scanner.l \
gcc -o a.out main.c hash.c -I.
lex: impossible to opne gcc
/usr/bin/m4:stdin:2994: ERROR: end of file in string
and
lex scanner.l
<tab> gcc -o a.out main.c hash.c -I.
error: missing separator.
The lex.yy.c generate by lex has is being included in the main file.
Thanks in advance,
Pedro
Try this:
lex.yy.c: scanner.l
lex scanner.l
comp: main.c hash.c
gcc -o a.out main.c hash.c -I.
main.c: lex.yy.c
The first rule set tells make that lex.yy.c needs to be rebuilt any time scanner.l changes and provides the command to recreate lex.yy.c. The second rule set tells make that the fake target comp depends on main.c and hash.c. If either file changes, then invoking make comp will cause a recompile. The last line is a stand-alone dependency that tells make to consider main.c as dirty any time that lex.yy.c changes. It will also force an invocation of make comp to create lex.yy.c if it does not exist.
all: a.out
lex.yy.c: scanner.l
lex scanner.l
a.out: lex.yy.c main.c hash.c
gcc -o a.out main.c hash.c -I.
Remove the backslash, or add a semicolon (;) before it.
As it is now, the two commands are added together on one line, and executed as one long command.
IIRC the usual Makefle pattern is
a.out: lex.yy.c main.c hash,c
<tab> gcc -o a.out main.c hash.c lex.yy.c -I. -ll
lex.yy.c: scanner.l
<tab> lex scanner.l
This is wrong, because in the original code, main.c includes lex.yy.c
This assumes the original code is changed so that main.c does not include lex.yy.c
Without that change, this will fail because there will be two definitions of yylex(), one from its #include in main.c, and one because it is supplied as a source code compilation unit. I encourage folks to not include a .c file into another .c file.
In general, the convention is to use a different file extension (.i) for included source files which generate unique symbols and code.
Related
I want to compile these files into executable.
//main.c
#include <stdio.h>
#include <mylib.h>
int main(void){
call_hello_world();
return 0;
}
//mylib.h
void call_hello_world(void);
//mylib.c
#include <mylib.h>
#include <stdio.h>
void call_hello_world( void ) {
printf( ”Hello world!” );
}
I tried
gcc -c -I. -fPIC -o mylib.o mylib.c
gcc -shared -o libmylib.so mylib.o
gcc -c -o main.o main.c
gcc -o hello main.o -L. -lmylib
but at the third step, I got stucked because it couldn't find my 'mylib.h'. My professor said I needed to change 'LD_LIBRARY_PATH' so I tried to add this export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/dev/shm my .zshrc but it still didn't work for me. Any suggestions what I should do?
There are several issues with your approach.
First, there is a difference between including a header file like this #include <mylib.h> and including it like that #include "mylib.h".
The first option is usually used to include standard library header files, that should be located in the standard set of directories according to the FHS on Linux.
The latter is the option you might want to use as it is usually used to include user-defined headers and tells the preprocessor to search in the directory of the file containing the directive. (See #quest49 answer's https://stackoverflow.com/a/21594/3852949)
The LD_LIBRARY_PATH environment variable is used to indicate where libraries should be searched for first before looking into the standard set of directories.
So what you would want to do to make your main.c file compile, and after changing #include <mylib.h> directive to #include "mylib.h", is to either :
Add the include file into the directory where your main.c file is located
Indicate where the include file path is with -I option to gcc
These are the commands needed :
gcc -c -I. -fPIC -o mylib.o mylib.c
gcc -shared -o libmylib.so mylib.o
gcc -c -I. -o main.o main.c
gcc -o hello main.o libmylib.so
Then in your shell:
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/full/path/of/directory/containing/libmylib-so
Here is my header file
#include <stdio.h>
#include <stdlib.h>
#include "gd.h"
#include "gdfontmb.h"
#include "gdfontl.h"
#include "gdfontg.h"
When I run this program I usually type 'gcc -o test test.o -lm -lpng -lgd'
It works fine for only one .c file, but this is just for testing. I want to link this with others c file in my project (Actually I'm really new to use gd.h)
Here is my Makefile (but It isn't work!!)
ifeq ($(OSTYPE),WINDOWS)
EXECEXT =.exe
COMP =__MINGCC__
PLATFORM =mingw
else
EXECEXT =
COMP =__GCC__
PLATFORM =linux
endif
EXECUTABLES= test$(EXECEXT)
all : $(EXECUTABLES)
test.o : test.c
gcc -c test.c
test$(EXECEXT) : test.o
gcc -o test$(EXECEXT) test.o -lm -lpng -gd
clean :
-rm *.o
-rm $(EXECUTABLES)
Using this Makefile, I got all error about undefined reference to whatever that are in the gd library.
What did I do wrong and How can I fix this?
Your own cc command already gives the answer. You need -lgd, not -gd.
E.g. set in the start:
LIBS=-lm -lpng -lgd
CC=gcc
(the latter can be the full OS-dependent path as well, and then the CC should be part of the OS specific part, and be specified as a full path).
and change the gcc line later to
$(CC) -o test$(EXECEXT) test.o $(LIBS)
And the rule for test.o is (usually) not really needed, as it is a default way to make a .o file from a .c file.
My instructions are:
The steps necessary to produce this program are:
Compile cpp2html.c to produce cpp2html.o. (Important: the source code in this project is C, not C++, and so must be compiled and linked with gcc, not g++.)
Run the command
flex cppscanner.l
to produce the file lex.yy.c from the language description in cppscanner.l.
Compile lex.yy.c to produce lex.yy.o. (This often produces a warning message about extra tokens. Ignore it.)
Link the .o files to produce an executable program named cpp2html
Write a makefile that will carry out these steps. Your makefile should result in only the minimum required amount of steps when any input file to this process is changed. (Note: you will probably not be able to base this makefile upon my self-updating makefile as in the earlier part of the assignment. Instead, you will probably find it necessary to write this one from scratch.
Here is my makefile:
cpp2html: cpp2html.o lex.yy.o
gcc -g -DDEBUG cpp2html.o lex.yy.o
mv a.out cpp2html
lex.yy.o: lex.yy.c
gcc -g -DDEBUG lex.yy.c
lex.yy.c:
flex cppscanner.l
cpp2html.o: cpp2html.c
gcc -g -DDEBUG cpp2html.c
What am I doing wrong here? I get an error message saying:
collect2: error: ld returned 1 exit status
make: *** [cpp2html.o] Error 1
Your makefile does not build 'cpp2html' when invoked:
gcc -g -DDEBUG cpp2html.c
This is due tonight, so any suggestions would be greatly appreciated.
It's complaining about the following:
cpp2html.o: cpp2html.c
gcc -g -DDEBUG cpp2html.c
This line is trying to compile cpp2html.c to a.out.
Change that to
cpp2html.o: cpp2html.c
gcc -g -DDEBUG -c cpp2html.c
Do the same thing for the line that compiles lex.yy.c to lex.yy.o. The -c option tells gcc to only generate the object file and write it to the .o file.
You can take advantage of other options and some built-in variables. Here's a suggestion:
cpp2html: cpp2html.o lex.yy.o
gcc -g -DDEBUG -o $# $?
$# evaluates to the name of the target. $? evaluates to the list of dependencies (the .o files). The -o option tells gcc to write the resulting binary to the specified file name instead of a.out.
You can also take advantage of implicit rules:
%.o : %.c
gcc -g -DDEBUG -c $<
This will build any .c file to the corresponding .o file, so you don't need to repeat the same commands for cpp2html.c and lex.yy.c.
Edit
FWIW, here's how I'd structure the makefile (with annotations; assumes Gnu make):
# Variables used by implicit rules
CFLAGS=-g -DDEBUG -Wall -Werror # flags for gcc
LFLAGS= # flags for flex, currently none
LEX=flex # lexer
CC=gcc # C compiler
# Variables to make life easier
LSRCS=cppscanner.l # All of our flex source files
SRCS=cpp2html.c $(patsubst %.l,%.c,${LSRCS}) # All of our C source files
OBJS=$(patsubst %.c,%.o,${SRCS}) # All of our object files
TARGET=cpp2html # Final target name
${TARGET} : ${OBJS}
${CC} ${CFLAGS} -o $# $^ # Explicit rule to build target
# $# expands to target name
# $^ expands to list of all prerequisites
clean:
rm -rf *.o $(patsubst %.l,%.c,${LSRCS})
That's it. We're relying on implicit rules to build the .l file to a .c file, and to build the .c files to .o files. The implicit rules use the LEX, CC, LFLAGS and CFLAGS variables to run the right commands with the right options. We only need the single explicit rule to build our final executable.
The advantage of structuring a makefile like this is that you can add files to the project without having to add new rules.
I think all of the above is correct; my main box is shut down at the moment so I can't test it. Refer to the Gnu Make manual for more details.
So I have to create a makefile that would generate the application described below and make sure each generated file has its own rule.
For the makefile:
The first tool is flex, which takes a file called spec.l and generates a file called lex.yy.c. Another tool called bison expects a file calledspec.y and will generate the file spec.tab.c. If bison is called using the directives -vd, it will also generate a file called spec.tab.h (which is needed when compiling lex.yy.c). The two C files can be compiled into object files and then linked together with the yacc (-ly) and lex (-ll) libraries to generate the compiler (a.out.
The makefile you describe must generate the following commands if you were starting just with spec.l and spec.y:
flex spec.l
bison -vd spec.y
gcc -c lex.yy.c
gcc -c spec.tab.c
gcc spec.tab.o lex.yy.o -ly -ll
i am not sure where to start with this problem
edit: what i have so far
compiler: spec.tab.o lex.yy.o
gcc spec.tab.o lex.yy.o -ly –ll
lex.yy.c: spec.l
flex spec.l
spec.tab.c: spec.y
bison -vd spec.y
spec.tab.o: spec.tab.c
gcc -c spec.tab.c
lex.yy.o: lex.yy.c spec.tab.h
gcc –c lex.yy.c
clean:
rm –f *.c *.o a.out
You have to tell the make about the dependencies. For example, lex.yy.c depends on spec.l:
lex.yy.c: spec.l
flex spec.l
The first line say lex.yy.c depends on spec.l. The second tells how to generate an updated version of lex.yy.c when spec.l is newer. We pretty much repeat that pattern with the other files. In the case of calledspec.y, we have two results that are produced from the same input/command. At least with GNU make, you can specify that like this:
spec.tab.c spec.tab.h: calledspec.y
bison -vd calledspec.y
Then you pretty much repeat the process for dependencies of .o (or .obj, etc.) files on headers and C files:
lex.yy.o: lex.yy.c spec.tab.h
$(cc) -c lex.yy.c
One final note: unless you specify otherwise, make will build the first target specified in the makefile, so you normally want to arrange it with the final executable first, and other targets after that:
parser: lex.yy.o y.tab.o
$(cc) -o parser lex.yy.o y.tab.o
lex.yy.o: lex.yy.c spec.tab.h
$(cc) -c lex.yy.c
And so on. This only applies to targets though, not to macros, so you'll typically see a few things like:
cflags = -O2
...at the beginning of a make file. Then the lines the invoke the compiler will use that, something like:
lex.yy.o: lex.yy.c spec.tab.h
$(cc) $(cflags) -c lex.yy.c
And when this is executed, the cflags macro will be expanded, so the command that gets executed is gcc -O2 -c lex.yy.c (and it predefines cc to the name of the compiler it normally expects to use, so Microsoft's make sets it to cl, GNU to gcc, etc.)
I am trying to make an object file via "cc -c -o " but I get the following statement ,what should I do to solve this,thanks in advance
~/hedor1>lex -t example.l > example.c
~/hedor1>cc -c -o example.o example.l
cc: example.l: linker input file unused because linking not done
the first line to produce the example.c is working and I get the .c file but when I write the second line I get the above!
You are passing the flex source to the compiler, which apparently interprets it as being a linker input file, and complains because you told the compiler not to do the linking step.
The second command should have been:
cc -c -o example.o example.c