getting error during make in ubuntu for procmon - c

$ make
gcc -Wall -D__KERNEL__ -DLINUX -DMODULE -O -I /lib/modules/`uname -r`/build/include/ -c -o procmon.o procmon.c
In file included from /lib/modules/3.0.0-12-generic/build/include/linux/kernel.h:13:0,
from procmon.c:22:
/lib/modules/3.0.0-12-generic/build/include/linux/linkage.h:5:25: fatal error: asm/linkage.h: No such file or directory
compilation terminated.
make: *** [procmon.o] Error 1
Im trying to compile using the make file of procmon system analysis module. I got the above message can any one help me out what is the problem?

you need to change your makefile like this:
obj-m :=procmon.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
install: all
rm -rf /dev/procmon
mknod /dev/procmon c 240 1
chmod 400 /dev/procmon
clean:
rm -f *.o
rm -f *~
rm -f a.out
rm -f test*
rm -f DEADJOE
dist: clean
cd .. ; tar cvzf procmon.tar.gz procmon
If you get any errors like devfs related, your procmon code will not work on recent kernels, you need to change the code accordingly

Related

GNU make, implicit rules not needed

I have the following directory:
Makefile
src/
main.c
dummy.raw
(main.o) (<- to be built)
(dummy.txt) (<- to be built)
build/
(main) (<- to be built)
And the following Makefile:
C_FILES=$(wildcard src/*.c)
O_FILES=$(C_FILES:%.c=%.o)
main: build/main
build/main: $(O_FILES)
gcc $(O_FILES) -o build/main
src/%.o: src/%.c src/dummy.txt
echo "Compiling using my rule"
gcc -c $< -o $#
src/%.txt: src/%.raw
touch $#
#echo "Created dummy file"
clean:
rm -f src/*.o
rm -f src/*.txt
rm -f build/*
The problem is that make seems to ignore my rule for producing .o files and use its own built-in version ; in particular, it does not build dummy.txt. Here's a sample output:
$ make clean
rm -f src/*.o
rm -f src/*.txt
rm -f build/*
$ make
cc -c -o src/main.o src/main.c
gcc src/main.o -o build/main
make only starts using the rule in the Makefile if I build the .txt file myself using make src/dummy.txt.
Why is make behaving this way?
How do I correct my Makefile to force make to build the intermediate dummy.txt?
Thanks!
The trouble is that your method invokes a chain of pattern rules, one to build src/main.o and one to build src/dummy.txt, and Make will prefer an implicit rule to a chain of pattern rules.
There are a couple of ways to solve this. Two simple ones:
You could invoke Make with the ‘-r’ a.k.a. ‘--no-builtin-rules’ option:
make -r
Or you could hard-code the rule for src/dummy.txt:
src/%.txt: src/%.raw
touch $#
#echo "Created dummy file"
src/dummy.txt: src/dummy.raw

Makefile missing separator error in spite of using the correct indentation

Although I have done some research about the error and understood that it has something to do with indentation. I still cannot figure out what is wrong with my Makefile which causes terminal to give error: Makefile:2: *** missing separator. Stop.
while running make clean command.
My Makefile has the content bellow:
obj-m := S3538332Device.o
KERNEL_DIR /usr/src/linux-headers-$(shell uname -r)
all:
$(MAKE) -C $(KERNEL_DIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o *.ko *.mod.* *.symvers *.order *~
I tried and ran cat -e -t -v {Makefile} to make sure that the tabs are at the right places:
obj-m := S3538332Device.o$
KERNEL_DIR /usr/src/linux-headers-$(shell uname -r)$
all:$
^I$(MAKE) -C $(KERNEL_DIR) SUBDIRS=$(PWD) modules$
clean:$
^Irm -rf *.o *.ko *.mod.* *.symvers *.order *~$
I am very new to makefile and c programming in general and I can't manage to find anything wrong with my code. Can anyone help me find out what the problem is that causes the error?
You're missing an assignment operator, it should be
KERNEL_DIR = /usr/src/linux-headers-$(shell uname -r)
or commonly KERNEL_DIR is usually only set if it's not already set:
KERNEL_DIR ?= /usr/src/linux-headers-$(shell uname -r)

error in generating .ko file for simple hello world module for linux kernel

I am a beginner in linux kernel development and trying to load a simple module in linux.
I have created an hello.c file, to be loaded as kernel module.
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("A Simple Hello World module");
static int __init hello_init(void)
{
printk(KERN_INFO "Hello world!\n");
return 0;
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Cleaning up module.\n");
}
module_init(hello_init);
module_exit(hello_cleanup);
this hello.c and the makefile both, I have kept in /home/linux/ directory.
makefile
obj-m +=hello.o
src= /usr/src/linux-headers-3.5.0-17-generic
all:
$(MAKE) -C $(src) SUBDIR-$(PWD) modules
clean:
rm -rf *.o *.ko
to generate .ko file, when I run the make command on terminal from the /home/linux directory , I get following error
h2o#h2o-Vostro-1015:~/linux$ make
make -C /usr/src/linux-headers-3.5.0-17-generic SUBDIR-/home/h2o/linux modules
make[1]: Entering directory `/usr/src/linux-headers-3.5.0-17-generic'
make[1]: *** No rule to make target `SUBDIR-/home/h2o/linux'. Stop.
make[1]: Leaving directory `/usr/src/linux-headers-3.5.0-17-generic'
make: *** [all] Error 2
kindly advise what am I missing or doing wrong..
Makefile
obj-m := hello.o # Module Name is hello.c
KDIR := /lib/modules/$(shell uname -r)/build
all: $(MAKE) -C $(KDIR) M=$(PWD) modules
clean: $(MAKE) -C $(KDIR) M=$(PWD) clean $(RM) Module.markers
modules.order
its not guaranteed that headers file will always be located in /usr/src directory, but it will surely be located in /lib/modules directory.
make sure that system has latest header files
to find out which header files to be present
run `
uname -r
on terminal, output will be like
3.5.0-17-generic
to install header files run
sudo apt-get install linux-headers-$(uname -r)
You have:
$(MAKE) -C $(src) SUBDIR-$(PWD) modules
But it seems like you want:
$(MAKE) -C $(src)/SUBDIR-$(PWD) modules
Or something along those lines; where does the source code live? You need to -C there.
Kernel build system is a bit complex. It would be good to read the kernel build process documentation. Which gives better understanding about, say,
Targets like --- modules / modules_install
Options like --- -C $KDIR / M=$PWD
Command Syntax ---
$ make -C <path_to_kernel_src> M=$PWD
$ make -C /lib/modules/uname -r/build M=$PWD
$ make -C /lib/modules/uname -r/build M=$PWD modules_install
Loadable module goals --- obj-m
etc...

Writing a makefile for modular project: Make

I am trying to learn makefile and below is my modular project structure:
$ pwd
/cygdrive/d/Make/Code
$ ls -R | grep ":$" | sed -e 's/:$//' -e 's/[^-][^\/]*\//--/g' -e 's/^/ /' -e 's/-/|/'
.
|-Build
|-Conversion
|---bin
|-----exe
|-----obj
|---include
|---lib
|---make
|---source
|-Main
|---bin
|-----exe
|-----obj
|---include
|---lib
|---make
|---source
|-Reverse
|---bin
|-----exe
|-----obj
|---include
|---lib
|---make
|---source
Three modules are 1)Conversion 2)Reverse 3)Main. makefile for each these modules are placed in respective make folder and they prepare corresponding .o files correctly and place them in bin/obj of respective folders.
Build directory is for generating the .exe file as shown below:
$ cat makefile
all:
cd ../Conversion/make; make
cd ../Reverse/make; make
cd ../Main/make; make
Conversion:
cd ../Conversion/make; make
Reverse:
cd ../Reverse/make; make
Main:
cd ../Main/make; make
exeApp:
cd ../Main/make; make App
cConversion:
cd ../Conversion/make; make clean
cReverse:
cd ../Reverse/make; make clean
cMain:
cd ../Main/make ; make clean
cleanAll:
cd ../Conversion/make; make clean
cd ../Reverse/make; make clean
cd ../Main/make; make clean
and the makefile for main is:
#VPATH= ./../source
INCLUDES= ./../include
OBJDIR= ./../bin/obj
EXEDIR= ./../bin/exe
OBJLOOKDIR= ./../../Conversion/bin/obj:./../../Reverse/bin/obj:./../../Main/bin/obj
#CONBIN= ./../../Conversion/bin/obj
#REVBIN= ./../../Reverse/bin/obj
#MAINBIN= ./../../Main/bin/obj
vpath %.h $(INCLUDES)
vpath %.o $(OBJLOOKDIR)
vpath %.c ./../source
CC= gcc
CFLAGS= -Wall -c -I$(INCLUDES)
OBJECTS= driver.o
PROJECTOBJECTS= binary.o hex.o octal.o reverseNum.o driver.o
main: $(OBJECTS)
driver.o: driver.c conversion.h
$(CC) $(CFLAGS) $< -o $(OBJDIR)/$#
App: $(PROJECTOBJECTS)
$(CC) -Wall $< -o $(EXEDIR)/$#
clean:
rm -rf $(OBJDIR)/*.o *~ $(EXEDIR)/*
But when I run make exeApp, I get below error:
$ make exeApp
cd ../Main/make; make App
make[1]: Entering directory '/cygdrive/d/Make/Code/Main/make'
gcc -Wall ./../../Conversion/bin/obj/binary.o -o ./../bin/exe/App
/usr/lib/gcc/i686-pc-cygwin/4.8.2/../../../libcygwin.a(libcmain.o): In function `main':
/usr/src/debug/cygwin-1.7.28-2/winsup/cygwin/lib/libcmain.c:39: undefined reference to `WinMain#16'
collect2: error: ld returned 1 exit status
makefile:26: recipe for target 'App' failed
make[1]: *** [App] Error 1
make[1]: Leaving directory '/cygdrive/d/Make/Code/Main/make'
makefile:17: recipe for target 'exeApp' failed
make: *** [exeApp] Error 2
Some how it is not being translated to below rule:
$ pwd
/cygdrive/d/Make/Code/Main/make
Gaurav#Gaurav-PC /cygdrive/d/Make/Code/Main/make
$ gcc -Wall ./../../Conversion/bin/obj/binary.o ./../../Conversion/bin/obj/hex.o ./../../Conversion/bin/obj/octal.o ./../../Reverse/bin/obj/reverseNum.o ./../../Main/bin/obj/driver.o -o Trial
Gaurav#Gaurav-PC /cygdrive/d/Make/Code/Main/make
$ ls
makefile makefileold Trial.exe
as The above rule compiles file, but exeApp rule translated only to gcc -Wall ./../../Conversion/bin/obj/binary.o -o ./../bin/exe/App . It should have been to gcc -Wall ./../../Conversion/bin/obj/binary.o ./../../Conversion/bin/obj/hex.o ./../../Conversion/bin/obj/octal.o ./../../Reverse/bin/obj/reverseNum.o ./../../Main/bin/obj/driver.o -o ./../bin/exe/App
I am not able to figure out why?
Can anyone help, Please.
Thanks

Device Driver Make file error

I have written the following make file ( basically to compile a device driver ) and i am not able to compile my code.
Here is my Makefile:
ifeq ($(KERNELRELEASE),)
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
# The current directory is passed to sub-makes as argument
PWD := $(shell pwd)
modules:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
abc: abc.c
gcc abc.c -o abc -lpthread
clean:
rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions abc
.PHONY: modules modules_install clean
else
# called from kernel build system: just declare what our modules are
obj-m := xyz.o
endif
I get the following error:
make -C /lib/modules/3.2.0-53-generic/build M=/home/some/something LDDINC=/home/some/something/../include modules
make[1]: Entering directory `/usr/src/linux-headers-3.2.0-53-generic'
make[2]: *** No rule to make target `/home/some/something/xyz.c', needed by `/home/some/something/xyz.o'. Stop.
make[1]: *** [_module_/home/some/something] Error 2
make[1]: Leaving directory `/usr/src/linux-headers-3.2.0-53-generic'
make: *** [modules] Error 2
It would be great if anybody could point out what are the errors that i might be doing

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