Device Driver Make file error - c

I have written the following make file ( basically to compile a device driver ) and i am not able to compile my code.
Here is my Makefile:
ifeq ($(KERNELRELEASE),)
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
# The current directory is passed to sub-makes as argument
PWD := $(shell pwd)
modules:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
abc: abc.c
gcc abc.c -o abc -lpthread
clean:
rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions abc
.PHONY: modules modules_install clean
else
# called from kernel build system: just declare what our modules are
obj-m := xyz.o
endif
I get the following error:
make -C /lib/modules/3.2.0-53-generic/build M=/home/some/something LDDINC=/home/some/something/../include modules
make[1]: Entering directory `/usr/src/linux-headers-3.2.0-53-generic'
make[2]: *** No rule to make target `/home/some/something/xyz.c', needed by `/home/some/something/xyz.o'. Stop.
make[1]: *** [_module_/home/some/something] Error 2
make[1]: Leaving directory `/usr/src/linux-headers-3.2.0-53-generic'
make: *** [modules] Error 2
It would be great if anybody could point out what are the errors that i might be doing

Related

Makefile missing separator error in spite of using the correct indentation

Although I have done some research about the error and understood that it has something to do with indentation. I still cannot figure out what is wrong with my Makefile which causes terminal to give error: Makefile:2: *** missing separator. Stop.
while running make clean command.
My Makefile has the content bellow:
obj-m := S3538332Device.o
KERNEL_DIR /usr/src/linux-headers-$(shell uname -r)
all:
$(MAKE) -C $(KERNEL_DIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o *.ko *.mod.* *.symvers *.order *~
I tried and ran cat -e -t -v {Makefile} to make sure that the tabs are at the right places:
obj-m := S3538332Device.o$
KERNEL_DIR /usr/src/linux-headers-$(shell uname -r)$
all:$
^I$(MAKE) -C $(KERNEL_DIR) SUBDIRS=$(PWD) modules$
clean:$
^Irm -rf *.o *.ko *.mod.* *.symvers *.order *~$
I am very new to makefile and c programming in general and I can't manage to find anything wrong with my code. Can anyone help me find out what the problem is that causes the error?
You're missing an assignment operator, it should be
KERNEL_DIR = /usr/src/linux-headers-$(shell uname -r)
or commonly KERNEL_DIR is usually only set if it's not already set:
KERNEL_DIR ?= /usr/src/linux-headers-$(shell uname -r)

Compilation error for Linux kernel module programming

I am learning Linux kernel module programming. I am using Beaglebone black for that. I have made simple 'Hello World' application and makefile. I have checked my makefile it's proper. But when I command 'make', it gives me following error:
root#beaglebone:/home/sonu# make
make: Warning: File `Makefile' has modification time 2.2e+02 s in the future
make -C /lib/modules/3.8.13-bone70/build M=/home/sonu modules
make: *** /lib/modules/3.8.13-bone70/build: No such file or directory. Stop.
make: *** [all] Error 2
Though I referred some websites. But, all they are asking me to install packages. As I am a newbie. I don't even know how to configure and start internet connection on Beaglebone using ethernet. Please help me I am stuck. Thanks in advance.
Code is:
#include<linux/module.h>
#include<linux/kernel.h>
#include<linux/init.h>
static int __init hello(void)
{
printk(KERN_INFO "Hello World!");
return 0;
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Bye");
}
module_init(hello);
module_exit(hello_cleanup);
Makefile is:
obj-m+=Hello.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
$(CC) Hello.c -o test
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
rm test
It appears that you're trying to build your module for a kernel version that you haven't installed the headers for.
Instead of calling uname directly in your rules, it's helpful to put that into a variable you can override:
obj-m+=Hello.o
KSRC := /lib/modules/$(shell uname -r)/build
all:
make -C $(KSRC) M=$(PWD) modules
$(CC) Hello.c -o test
clean:
make -C $(KSRC) M=$(PWD) clean
rm test
Now, you can override with the actual location of your kernel headers:
make KSRC=/usr/src/linux-headers-4.9.2 all
You can simplify the Makefile further with a catch-all rule:
obj-m+=Hello.o
KSRC := /lib/modules/$(shell uname -r)/build
all: modules
$(CC) Hello.c -o test
%:
make -C $(KSRC) M=$(PWD) $#
clean::
make -C $(KSRC) M=$(PWD) clean
$(RM) test

Build Linux Kernel Module using Makefile with different pathname

I am trying to compile a Linux kernel module using the standard example Makefile specified in the Linux Kernel Module Programming Guide. If the Makefile is called Makefile, then everything works. If I rename the Makefile to Makefile.hello or something else, then it fails as it cannot find the path Makefile. I was wondering if there is a command or set of flags I can add to my Makefile to make this function properly. I need to rename the Makefile as I am calling it from CMake. Cmake creates its own Makefiles and will commonly overwrite what I already have.
I replaced my kernel module code with the hello world example and replicated the problem. I know its the makefile.
hello world example hello.c
/*
* hello−1.c − The simplest kernel module.
*/
#include <linux/module.h> /* Needed by all modules */
#include <linux/kernel.h> /* Needed for KERN_INFO */
int init_module(void)
{
printk(KERN_INFO "Hello world 1.\n");
/*
* A non 0 return means init_module failed; module can't be loaded.
*/
return 0;
}
void cleanup_module(void)
{
printk(KERN_INFO "Goodbye world 1.\n");
}
Makefile
obj-m += hello.o
ifeq (,$(KDIR))
KDIR := /lib/modules/$(shell uname -r)/build
endif
PWD := $(shell pwd)
all:
$(MAKE) -C $(KDIR) M=$(PWD) $(KCONFIG) modules
clean:
$(MAKE) -C $(KDIR) M=$(PWD) clean
If makefile is called Makefile. (Successfully builds)
$> make -f Makefile
make -C /lib/modules/4.4.0-21-generic/build M=/home/msmith/Desktop/kernel-test modules
make[1]: Entering directory '/usr/src/linux-headers-4.4.0-21-generic'
CC [M] /home/msmith/Desktop/kernel-test/hello.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/msmith/Desktop/kernel-test/hello.mod.o
LD [M] /home/msmith/Desktop/kernel-test/hello.ko
make[1]: Leaving directory '/usr/src/linux-headers-4.4.0-21-generic'
Make output if makefile is called Makefile.hello (Fails to build)
$> make -f Makefile.hello
make -C /lib/modules/4.4.0-21-generic/build M=/home/msmith/Desktop/kernel-test modules
make[1]: Entering directory '/usr/src/linux-headers-4.4.0-21-generic'
scripts/Makefile.build:44: /home/msmith/Desktop/kernel-test/Makefile: No such file or directory
make[2]: *** No rule to make target '/home/msmith/Desktop/kernel-test/Makefile'. Stop.
Makefile:1396: recipe for target '_module_/home/msmith/Desktop/kernel-test' failed
make[1]: *** [_module_/home/msmith/Desktop/kernel-test] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-4.4.0-21-generic'
Makefile.hello:10: recipe for target 'all' failed
make: *** [all] Error 2
I tried adding the -f to the internal MAKE parameters, however that just caused more issues.
Move all Kbuild-related logic into the file Kbuild. Kernel's build system checks file with this name first, so it won't look into Makefile, created by CMake. This feature is documented in Documentation/kbuild/makefiles.txt.
I use exactly this approach in my CMake projects, related with Linux kernel.
Open script/Makefile.build into kernel tree:
41 # The filename Kbuild has precedence over Makefile
42 kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
43 kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
44 include $(kbuild-file)
This part of code (43-44) include Makefile with name 'Makefile'.
The default Makefile. Name = Makefile ... and Makefile-hello, or Makefile.hello.
obj-m := hello.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) M=$(PWD) clean
$ make : OK
$ make -f Makefile-hello OK
$ make -f Makefile.hello Also OK.
Your Makefile : $ make -f Makefile.msmith OK, no errors.

Empty Module.symvers file when compiling a module

I'm writing a custom kernel module (let's call it mod1) that I would like to export functions for use in other modules (let's call those mod2, etc...). When compiling the other modules, I get warning messages about undefined symbols (functions in mod1). Though everything should work fine after loading, I like to compile without warnings. I read that I should add the path to mod1's Module.symvers to KBUILD_EXTRA_SYMBOLS However, I noticed that my Module.symvers file is empty. What am I doing wrong?
Here's a MWE of a module:
#include <linux/module.h>
MODULE_INFO(version, "0.1");
MODULE_AUTHOR("Me");
MODULE_LICENSE("GPL");
int foo(int x) {
return x;
}
EXPORT_SYMBOL_GPL(foo)
And a Makefile:
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
And me running make showing that Module.symvers is empty:
user#host:~/mwe$ make; [[ -s ./Module.symvers ]] || echo "File size is zero!"
make -C /lib/modules/3.13.0-30-generic/build M=/home/user/mwe modules
make[1]: Entering directory `/usr/src/linux-headers-3.13.0-30-generic'
Building modules, stage 2.
MODPOST 0 modules
make[1]: Leaving directory `/usr/src/linux-headers-3.13.0-30-generic'
File size is zero!
I'm not sure what I'm doing wrong and my search for answers has been fruitless thusfar.
Looks like the Makefile is incorrect. Where is the name of the file you want to compile ? Change test.o to whatever your filename.
Makefile:
obj-m += test.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

getting error during make in ubuntu for procmon

$ make
gcc -Wall -D__KERNEL__ -DLINUX -DMODULE -O -I /lib/modules/`uname -r`/build/include/ -c -o procmon.o procmon.c
In file included from /lib/modules/3.0.0-12-generic/build/include/linux/kernel.h:13:0,
from procmon.c:22:
/lib/modules/3.0.0-12-generic/build/include/linux/linkage.h:5:25: fatal error: asm/linkage.h: No such file or directory
compilation terminated.
make: *** [procmon.o] Error 1
Im trying to compile using the make file of procmon system analysis module. I got the above message can any one help me out what is the problem?
you need to change your makefile like this:
obj-m :=procmon.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
install: all
rm -rf /dev/procmon
mknod /dev/procmon c 240 1
chmod 400 /dev/procmon
clean:
rm -f *.o
rm -f *~
rm -f a.out
rm -f test*
rm -f DEADJOE
dist: clean
cd .. ; tar cvzf procmon.tar.gz procmon
If you get any errors like devfs related, your procmon code will not work on recent kernels, you need to change the code accordingly

Resources