Is it possible to compile svdlibc on a mac (64 bit)? - c

I'm trying to compile svdlibc on a 64 bit mac. Running the make file returns the error message:
main.c:1: error: CPU you selected does not support x86-64 instruction set
main.c:1: error: CPU you selected does not support x86-64 instruction set
make: *** [main.o] Error 1
Which doesn't make much sense.
The make file is:
# Linux or Windows:
CC = gcc -Wall -O4 -march=i486
# CC = icc -w1 -O3 -march=i486
# Macintosh:
ifeq ($(HOSTTYPE),powerpc)
CC = cc -pipe -O3 -Wall -fno-common -arch ppc
endif
LIBS=-lm
OBJ=svdlib.o svdutil.o las2.o
svd: Makefile main.o libsvd.a
${CC} ${CFLAGS} -o svd main.o libsvd.a ${LIBS}
mv -f $# ${HOSTTYPE}/$#
ln -s ${HOSTTYPE}/$# $#
main.o: Makefile main.c svdlib.h
${CC} ${CFLAGS} -c main.c
libsvd.a: ${HOSTTYPE} ${OBJ}
rm -f $# ${HOSTTYPE}/$#
ar cr $# ${OBJ}
ranlib $#
mv -f $# ${HOSTTYPE}/$#
ln -s ${HOSTTYPE}/$# $#
svdlib.o: Makefile svdlib.h svdlib.c
${CC} ${CFLAGS} -c svdlib.c
svdutil.o: Makefile svdutil.c svdutil.h
${CC} ${CFLAGS} -c svdutil.c
las2.o: Makefile las2.c svdlib.h svdutil.h
${CC} ${CFLAGS} -c las2.c
clean:
rm *.o
$(HOSTTYPE):
if test ! -d $(HOSTTYPE); \
then mkdir $(HOSTTYPE); fi
Editing the make file to alter the -march flag lets the compilation proceed but apparently the linking fails with:
ld: lto: could not merge in main.o because Invalid ALLOCA record for
architecture x86_64
Has anyone done this? Or is there a different svd library that I should use instead? (For large sparse matrices?)
EDIT: porneL seems to have found the problem. Changing the top line in the makefile to:
CC = gcc -Wall -O3 -march=x86-64
compilation work. Haven't tested the results yet, but looks very promising.

-O4 causes this for some reason. Use -O3 instead.

You could try with port ( http://www.macports.org/ ) it seems it s availablee :
svdlibc #1.34 (math, science)
SVDLIBC is a C library to perform singular value decomposition
Basically you ll install macports then , sudo port install svdlibc.

Related

Clang error on makefile execution of make

So I have two C files which are master.c, slave.c and then config.h and I'm trying to build a makefile for the execution of these files and I'm getting an error.
I'm using a normal terminal on MacOS and when executing make I get the following error:
ss#US3FHIM0XQ86TJG: ~/project-2[master*]$ make
gcc -o master config.h master.c -g -I -std=gnu99
clang: error: cannot specify -o when generating multiple output files
make: *** [master] Error 1
Here is what my makefile looks like:
CC = gcc
CFLAGS = -g -I -std=gnu99
all: master slave
master: config.h master.c
$(CC) -o $# $^ $(CFLAGS)
slave: config.h slave.c
$(CC) -o $# $^ $(CFLAGS)
clean:
rm master slave cstest logfile.*
Can someone spot what might be causing this issue?
Remove config.h. You can compile it on the command line and omit "config.h", ie:
gcc -o master master.c -g -I -std=gnu99
Some people like to put that -o at the end:
gcc -g -I -std=gnu99 -c master.c -o master
A more appropriate way would be:
gcc -g -I/usr/include -std=gnu99 -c master.c -o master
Generally, the -I has a path, such as -I/usr/include, but you can omit the -I as your compiler usually looks there first.
Also, you may have to tweak your Makefile and omit the config.h if it is happening when you type make.
Some little errors you can fix by compiling the object by hand (ie, as above, gcc -g -I/usr/include -std=gnu99 -c master.c -o master)
Once you edit Makefile and remove config.h, and perhaps use -I/usr/include or path to your headers, you can run:
make clean
make all
or just:
make slave
or:
make master
etc, etc
$^ is a placeholder for the list of dependencies. That is why the rule
master: config.h master.c
$(CC) -o $# $^ $(CFLAGS)
runs the command
gcc -o master config.h master.c -g -I -std=gnu99
Compiling .h produces one output, compiling .c produces another output. The compiler does not know to which of them to apply -o. The proper way is using rules
master: master.c config.h
$(CC) -o $# $< $(CFLAGS)
slave: slave.c config.h
$(CC) -o $# $< $(CFLAGS)
$< is a placeholder for the first item in the list of dependencies. These rules run gcc properly
gcc -o master master.c -g -I -std=gnu99
gcc -o slave slave.c -g -I -std=gnu99

I want to compile my code to 32 bit systems and have the following make file, how do I make it right?

So, I got this Makefile from a git repository and it compiles the source code that came with this correctly. The project is for an Operating System from scratch. This Makefile is for a 64-bit OS tutorial. I'm currently learning about 32-bit operating systems and I don't want to jump into the long mode for now. My project compiles correctly with this makefile but it never loads the kernel into memory. I think I should change the CCFLAGS = -ggdb -c -ffreestanding -target x86_64-none-elf to some other flags. How do I go about this. I already tried install i386-elf-gcc using brew but it's giving me a lot of errors. Any help would be appreciated. Thanks :)
CC = clang
GDB = gdb
LD = ld.lld
ASM = nasm
INC = -Iinc/
SRC = $(shell find . -type f -name "*.c")
ASM_SRC = $(shell find . -type f -name "*.asm")
# CRITICAL: assembly must be linked first
OBJ = ${ASM_SRC:.asm=.o} ${SRC:.c=.o}
CCFLAGS = -ggdb -c -ffreestanding -target x86_64-none-elf
LDFLAGS = -Ttext 0x8200
LDFLAGS_BIN = ${LDFLAGS} --oformat binary
LDFLAGS_ELF = ${LDFLAGS} --oformat binary --entry main
ASFLAGS = -f elf64
all: kernel kernel.elf
kernel: ${OBJ}
#${LD} -o $# ${LDFLAGS_BIN} $^
kernel.elf: ${OBJ}
#${LD} -o $# ${LDFLAGS_ELF} $^
%.o: %.c
#${CC} ${CCFLAGS} ${INC} -o $# $^
%.o: %.asm
#${ASM} $< ${ASFLAGS} -o $#
clean:
#rm -f kernel kernel.elf *.o **/*.o

make: the system cannot find the file specified (Error 2)

I'm trying to compile a C program on Windows for use on a linux dev board.
When I try to compile using a makefile I get this output:
$ make
arm-linux-gnueabihf-gcc -g -Wall main.c -o filetest
process_begin: CreateProcess(NULL, arm-linux-gnueabihf-gcc -g -Wall main.c -o filetest, ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [filetest] Error 2
This happens whether or not a blank file called filetest is present or not in the same directory. If it is present, I can run make clean and it will remove the file.
Here is the makefile I'm using:
#
TARGET = filetest
ALT_DEVICE_FAMILY ?= soc_cv_av
SOCEDS_ROOT ?= $(SOCEDS_DEST_ROOT)
HWLIBS_ROOT = $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib
CROSS_COMPILE = arm-linux-gnueabihf-
CFLAGS = -g -Wall -D$(ALT_DEVICE_FAMILY) -I$(HWLIBS_ROOT)/include/$(ALT_DEVICE_FAMILY) -I$(HWLIBS_ROOT)/include/
LDFLAGS = -g -Wall
CC = $(CROSS_COMPILE)gcc
ARCH= arm
build: $(TARGET)
#
$(TARGET):main.c
$(CC) $(LDFLAGS) $^ -o $#
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -f $(TARGET) *.a *.o *~
I used tabs in my actual makefile instead of spaces for the code block above ^^
Also, I'm working within Intel's FPGA SoC EDS for a Cyclone V board.

Makefile undefined reference to library

I know this is a very common question, but no matter where I looked I couldn't find a solution that worked.
I am writing an OS, and am also writing my own version of the c standard library, purely as a general interest type thing. I have my c standard library, which currently consists only of an incomplete string.h, in the sb_libc folder in the kernel's main directory. I can't use make to actually make the kernel if it includes my string.h header. I keep getting "undefined reference to strcpy". In order to test if I could include anything, I wrote two additional files, io.c and io_asm.s, and put their *.o files into the kernel's main directory. I can link those with the kernel just fine. Clearly, my library search paths are wrong in my make file. I'll post it below. If anyone can give me an idea on what I'm doing wrong, that would be great.
OBJECTS = loader.o io.o io_asm.o kmain.o ./sb_libc/string.o
CC = gcc
CFLAGS = -e kmain -m32 -nostdlib -nostdinc -fno-builtin -fno-stack-protector -nostartfiles -nodefaultlibs -Wall -Wextra -Werror -c -I./sb_libc/ -L./sb_libc/
LDFLAGS = -T link.ld -melf_i386 -I./sb_libc/ -L./sb_libc/
AS = nasm
ASFLAGS = -f elf
all: kernel.elf
kernel.elf: $(OBJECTS)
ld $(LDFLAGS) $(OBJECTS) -o kernel.elf
os.iso: kernel.elf
cp kernel.elf iso/boot/kernel.elf
genisoimage -R -b boot/grub/stage2_eltorito -no-emul-boot -boot-load-size 4 -A os -input-charset utf8 -quiet -boot-info-table -o os.iso iso
run: os.iso
bochs -f bochsrc.txt -q
%.o: %.c
$(CC) $(CFLAGS) $< -o $#
%.o: %.s
$(AS) $(ASFLAGS) $< -o $#
clean:
rm -rf *.o kernel.elf os.iso

Makefile: No rule to make target despite giving target?

While trying to use Make I get the following error:
make: *** No rule to make target `paging.c', needed by `obj/paging.o'. Stop.
But I have given the makefile the rule for making the target. Here's my makefile:
--------
C_SOURCES= main.c monitor.c common.c descriptor_tables.c timer.c paging.c \
fs.c initrd.c task.c syscall.c --------
S_SOURCES= boot.s interrupt.s gdt.s process.s
C_OBJECTS=$(patsubst %.c, obj/%.o, $(C_SOURCES))
S_OBJECTS=$(patsubst %.s, obj/%.o, $(S_SOURCES))
CFLAGS=-c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders
LDFLAGS=-Tlink.ld -melf_i386 --oformat=elf32-i386
ASFLAGS=-felf
all: kern/kernel
.PHONY: clean
clean:
-rm -f obj/*.o kern/kernel
kern/kernel: $(S_OBJECTS) $(C_OBJECTS)
ld $(LDFLAGS) -o $# $^
$(C_OBJECTS): obj/%.o : source/%.c
gcc $(CFLAGS) $< -o $#
vpath %.c source
$(S_OBJECTS): obj/%.o : %.s
nasm $(ASFLAGS) $< -o $#
vpath %.s asem
NOTE: the -------- is not in the original makefile, they are just used to pick the rule I have used.
make output:
nasm -felf asem/boot.s -o obj/boot.o
nasm -fenasm -felf asem/boot.s -o obj/boot.o
nasm -felf asem/interrupt.s -o obj/interrupt.o
nasm -felf asem/gdt.s -o obj/gdt.o
nasm -felf asem/process.s -o obj/process.o
gcc -c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders source/main.c -o obj/main.o
gcc -c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders source/monitor.c -o obj/monitor.o
gcc -c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders source/common.c -o obj/common.o
gcc -c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders source/descriptor_tables.c -o obj/descriptor_tables.o
gcc -c -nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders source/timer.c -o obj/timer.o
make: *** No rule to make target `source/paging.c', needed by `obj/paging.o'. Stop.
Why is it coming out with the error despite giving it what it needs?
You will have to change the line
$(C_OBJECTS): obj/%.o : %.c
to
$(C_OBJECTS): obj/%.o : source/%.c
edit, in reflect of question change:
void page_fault(registers_t regs)
void page_fault(registers_t *regs);
Compare ;) The two should be the same. According to the code chunk from paging.c, the version in paging.h should be corrected (just remove the *).
Does the file paging.c exist in the same directory as the Makefile?
If it does not, Make will look for a rule to create it. Since there is no rule to create paging.c, it will give you this error.
The error is telling you that "make" cannot find the file "paging.c" anywhere in the vpath or in the current directory, and it has no rule to create "paging.c" from any other source file.
Make sure that you actually have "paging.c" where you think you do, and that it is actually called "paging.c" and not "paging.c " (extra space) or some other unicode special stuff that looks like "paging.c" when you print it out, but isn't.

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