I found this rm command in a Makefile.
rm -f $(ODIR)/*.o *~ $(PROG) $(INCDIR)/*~
What is the meaning of *~?
*~ is not special. It matches files that end with the ~ character (often editor backup files).
emacs is one program which leaves files ending with ~ around as backup files. So the creator of the makefile was probably an emacs user who wanted this target (perhaps clean?) to clean up .o files and executables and emacs droppings.
It means all files with a ~ at the end, no matter what the other letters of the filename are. These are usually temporary files.
Related
With the Makefile I'm working on, I convert pdf files into txt files.
I've implemented a clean target that would remove all .txt files. However, I do not wish to delete the source files, only those that have been generated.
Example:
I have following files in my folder:
pdfsource.pdf and donotharm.txt
Running my makefile would create following file:
pdfsource.txt
For now, my clean looks like this:
rm -f *.txt
Using make clean would not only delete pdfsource.txt, which is desired, but also donotharm.txt.
I think I could use: .PRECIOUS: donotharm.txt, but this is really specific. I'd like to have a general solution to this.
Thanks in advance!
You can list the generated files in a make variable and use it to clean only these:
PDF := $(wildcard *.pdf)
TEXT := $(patsubst %.pdf,%.txt,$(PDF))
...
clean:
rm -f $(TEXT)
Or, if you prefer a more compact (but a bit less readable) form:
clean:
rm -f $(patsubst %.pdf,%.txt,$(wildcard *.pdf))
Of course, this works only if there is no {foo.pdf,foo.txt} pair for which you want to preserve foo.txt from deletion by make clean.
Note: using make variables, in such a case, is usually a good idea because they can be shared among various rules. Example:
PDF := $(wildcard *.pdf)
TEXT := $(patsubst %.pdf,%.txt,$(PDF))
.PHONY: all clean
all: $(TEXT)
$(TEXT): %.txt: %.pdf
pdftotext $< $#
clean:
rm -f $(TEXT)
Another approach: "make -nps" gives you all make's metadata about dependencies. For any intermediate file, it prints
filename: ...
So you can exactly delete such files with a generic "clean" rule:
clean:; MAKEFLAGS= ${MAKE} -j1 -spinf $(word 1,${MAKEFILE_LIST}) \
| sed -n '/^# I/,$${/^[^\#\[%.][^ %]*: /s/:.*//p;}; 1s|.*|${clean}|p' | xargs rm -rf
The first line handles use of makefiles other than the defaults (makefile, GNUmakefile, Makefile)
In the "sed" command:
/^# I/,$
... selects the zone of make metadata with dependencies.
/^[^\#\[%.][^ %]*: /
... filters out comments, implicit rules, and files with no dependencies (the trailing space). It doesn't filter out phony targets; oh well.
Finally:
1s|.*|${clean}|p
adds any explicit targets for "clean" -- what you know that make does not; e.g.
clean += tmpdir/* *.gcda
Hello!
I want to make Makefile.win which will make a tar.gz with 2 other files(dodaj.c and another Makefile, both are in the same directory where i want use commend make ).My problem is
make dodaj.tar.gz
make: *** No rule to make target 'dodaj.tar.gz'. Stop
Here is my code:
dodaj.tar.gz: dodaj.c Makefile
mkdir dodaj-434686
cp ./dodaj.c ./dodaj-434686
cp ./Makefile ./dodaj-434686
tar -czvf dodaj.tar.gz ./dodaj-43468
rm -rf ./dodaj-434686
Make will look for files named 'makefile' and 'Makefile'. If you are using Gnu make, it will also look for 'GNUmakefile'. It does not look for 'Makefile.win'. To use that file, you must do make -f Makefile.win dodaj.tar.gz
I am writing(at first time) a makefile for my program in C. This is my make file:
CC = gcc
FILES = in_one.c in_two.c in_two.h
OUT_EXE = out_executable
build: $(FILES)
$(CC) -o $(OUT_EXE) $(FILES)
clean:
rm -f *.o core
rebuild: clean build
Actually, everything works properly : Gcc compiler doesn't show any errors, but maybe someone could explain what does these lines mean:
clean:
rm -f *.o core
rebuild: clean build
The clean lines say that if you want to make clean it does not depend on anything (nothing behind ":"). Furthermore the rm command deletes all object files.
The rebuild: clean build says that if you want to make rebuild it depends on clean and build. So the first thing to do is clean (= delete all object files) and then make build (= compile all source files). After that there is nothing more to do so make stops.
For a quick start, make recipes have the following syntax:
target: dependency1 dependency2 ... dependencyN
command1
command2
...
command3
So if target needs to be made at first all dependencies (dependency1 - dependencyN) are made. After this is done command1 - commandN are executed in that order.
You are rm (removing) or deleting all (*) the existing .o Files. So the next time you compile or call the make file you are just left with the new ones.
Build: $(Files) is creating the .o so the compiler can link them together into an executable
http://puu.sh/7OiDL.png
Ok so what does export: StackImplementation.o do? Like where does it export that to?
Also, what is gcc -l doing? I googled it and it says "gcc -l links with a library file". What's linking to the library file?
Lastly, what does "substitute a print command of your choice for lpr below" mean? What's lpr do? and what's clean: rm -f *.o?
The export is the name of a phony target. You can say
% make export
And make will build the its dependencies. There is no action specifying how to convert the dependencies into a file called export, and in the absence of an implicit rule, the make will stop after building the dependencies.
The -I to gcc is adding a path to search for include files. You are confusing it with the -l option which specifies the name of a library to link (a pre-built collection of object files from which unresolved symbols can be satisfied).
The lpr command sends a file to the default line printer. Again, print is a phony target; doing
% make print
sends the source file to the printer.
Most makefiles include a clean rule to delete generated files. It is necessary when the dependencies are not properly specified, and a change to a source file does not cause the target to be built. The rm command is short for remove; it deletes files. If you do
% make clean
it will force-delete all files that end with .o.
Most of these targets are phony, and will not work correctly if there happen to be files with those names that are newer than their dependencies (if any). Most makes allow you to specify which targets are phony by listing them as dependencies of a super phony .PHONY target. Make will then ignore the filesystem, and will always apply the rules.
export:
this is a target named "export" and is the first target in the makefile so it will get called by default if no target is specified on the command line. Not clear to me why it is called "export" but that's the name somebody chose for it
export: StackImplementation.o
this says that export depends on StackImplementation.o so it will invoke the target StackImplementation.o when export is invoked
StackImplementation.o: StackImplementation.c ...
StackImplementaiton.o depends on the source file StackImplementation.c and the include files listed. This will run gcc which has the flag -I../Include which tells gcc to include .h files in adjacent directory "Include"
# substitute...
this is a comment indicating to change the print command lpr to some other print command if you want to
clean:
this is a common target that will delete object files with the -f option, forcing remove even if write permission is not set
1) lpr submits files for printing. Files named on the command line are sent to the named printer
(or the default destination if no destination is specified). If no files are listed on the com‐
mand-line, lpr reads the print file from the standard input.
for more information about "lpr " use user manual of linux.
2)gcc -l link external library to your program if any dependency .
example::
gcc hello.c -o hello -lpthread -ldrm -ldrm_omap
in Make file::
clean:
rm -rf *.o
here clean is a rule of make and when we call make clean then it will invoke rm -rf *.o to remove all object files.
I've just started to learn C (using Thinking In C) and I'm wondering about what files I should be ignoring in a C project's git repository.
No suggestion can be too obvious -- I'm a total noob. Thanks!
I guess there will be a few generated files that you don't wan't to be sticking in your repo (assuming your build output dir is in your git heirachy):
object files (.o, o.obj)
libraries (.lib)
DLLs, shared objects (.so, .dll)
Executables (.exe, a.out ?)
GIT ignore files are something I tend to do iteratively. "Hey, I don't need those things in my repo" ...
Edit: re dmckee's comment
Yep, you definately want to be ignoring swap files, temp files etc. I have the following as a baseline for my .gitignore:
*.swp
.~
thumbs.db
You can also setup your build to happen in a subdirectory say build and then you can ignore the whole thing inside .gitignore
build/
And you're done.
I use this in my .gitignore
But I am building for micro-controllers, so I don't know if it helps you much.
The easiest way to know, is just do a make clean, then add all your files, then do a make all and see what extra stuff appears.
#Some of these are related to eclipse. So i keep them out of my repo
.cproject
.dep/
.project
.settings/
#files being edited
*~
# make and build files
*.lst
*.o
*.eep
*.lss
*.map
*.sym
# I keep these, since I prefer having the reference of the final build
# *.elf
# *.hex
Github's .gitignore file templates cover most of the common files for projects in a variety of languages.
The C .gitignore template looks like this:
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf
Using a *nix system and a Makefile, you could add each generated file to .gitignore.
As an example I use the following when creating an executable from a single source (Example for a C executable generation):
%: %.c
gcc -o $# $<
grep '^$#$$' .gitignore > /dev/null || echo '$#' >> .gitignore
The following line can be added to other recipes to add target $# to .gitignore file:
grep '^$#$$' .gitignore > /dev/null || echo '$#' >> .gitignore
Explanation:
grep '^$#$$' .gitignore : searches for the target in .gitignore
^ indicates start of line
$$ is a single $ (but Makefile needs $$ to work) and indicates the end of the line
'^$#$$' represents the target name
|| : executes the next command only if the left hand one failed
so only if grep ... does not find the target name in .gitignore, echo ... is executed
echo '$#' >> .gitignore: adds the target name to .gitignore
Eventually, you will add to clean and rebuild everything to make sure all files are correctly ignored