I have two Makefiles under one directory. One is called "Makefile", another is called "Makefile.coverage". However, "make" can only execute the "Makefile". How can I execute what's in "Makefile.coverage"?
From the make manual:
The way to specify the name of the makefile is with the ‘-f’ or ‘--file’ option (‘--makefile’ also works). For example, ‘-f altmake’ says to use the file altmake as the makefile.
So in your example it would be
make -f Makefile.coverage
Related
I was trying to execute Makefile and wanted to execute a C program with it. First, how can I include test.c file for makefile?
I've placed makefile in root directly as there will be other .c files later added.
Can anyone hep me executing this?
File structure:
Makefile code so far not working (it will work if I place it inside src still not getting the output of file.)
# -o : object file
Test: test.c
gcc -o Test test.c
Glad if anyone can help or suggest anything!
I don't usually follow links but I was curious so I did so. Your problem isn't related to make or makefiles or how your code is built. As best as can be determined from the screenshots, all that is fine.
The problem is that when you try to run the program, it's not found.
When the shell tries to run a program it looks in the directories contained in the PATH environment variable, and only there. It won't look in the current directory, unless the current directory is on the PATH.
So when you type the name of a program without a pathname to tell the shell where to find it, such as Test (by the way it's not a good idea to call your program Test because there is a system program named test on POSIX systems and it can cause confusion), it will search the directories on PATH for Test, and if the program is not found there it will fail.
If you don't want to rely on PATH you need to give the shell the pathname of the program you want to run. So you can run .\Test instead (on POSIX systems it would be ./Test), to tell the shell that you want to run Test from the current directory.
Most Linux apps are compiled with:
make
make install clean
As I understand it, the make command takes names of build targets as arguments. So for example install is usually a target that copies some files to standard locations, and clean is a target that removes temporary files.
But what target will make build if no arguments are specified (e.g. the first command in my example)?
By default, it begins by processing the first target that does not begin with a . aka the default goal; to do that, it may have to process other targets - specifically, ones the first target depends on.
The GNU Make Manual covers all this stuff, and is a surprisingly easy and informative read.
To save others a few seconds, and to save them from having to read the manual, here's the short answer. Add this to the top of your make file:
.DEFAULT_GOAL := mytarget
mytarget will now be the target that is run if "make" is executed and no target is specified.
If you have an older version of make (<= 3.80), this won't work. If this is the case, then you can do what anon mentions, simply add this to the top of your make file:
.PHONY: default
default: mytarget ;
References:
https://www.gnu.org/software/make/manual/html_node/How-Make-Works.html
GNU Make also allows you to specify the default make target using a special variable called .DEFAULT_GOAL. You can even unset this variable in the middle of the Makefile, causing the next target in the file to become the default target.
Ref: The Gnu Make manual - Special Variables
bmake's equivalent of GNU Make's .DEFAULT_GOAL is .MAIN:
$ cat Makefile
.MAIN: foo
all:
#echo all
foo:
#echo foo
$ bmake
foo
See the bmake(1) manual page.
I have written a c program. I want to pipe the program and I want to make it look meaningful. So instead of writing ./a.out each time, I want to name it changetext. To achieve that, I compiled my program following way: gcc -o changetext myprog.c. To the best of my knowledge, this should replace the use of ./a.out and changetext should do that instead. But I'm getting command not found. I am new to c and unix environment. Any suggestion appreciated.
As I said in a comment, you can either put a dot slash (./) in front of the executable to run it
./changetext
Or you put in in a directory that is referenced in the PATH environment variable. A nice explanation of this safety feature can be found here (thanks to rubenvb):
http://www.linfo.org/dot_slash.html
It says that this is more or less to distinguish built-in commands from user-written commands with the same name. I am not convinced though. The shell could simply prefer built-in names to user-supplied ones, and look in the current directory as well as in the PATH.
But this is the *nix way.
In order to compile and run a program such as your changetext with just the command chanhetext, you must put the binary in a directory listed in your PATH environment variable. It is recommended that you put programs that you made for your own use in the ~/bin/ directory. The command you would use to accomplish this would be the following, assuming ~/bin/ already exists:
gcc -o ~/bin/changetext myprog.c
If it does not exist, you can simply create it, then log out and back in.
If you are tired of doing the ./ before the program name you can always make an alias such as
alias a='./a.out' or alias changetext='./changetext'
this just basically look for everytime you type changetext or a and then replaces it to have the ./ infront of it
I am new in Makefile. I have wrote hello.c and when I do "make hello" then it gives executable named as "hello". Internally it showing "cc hello.c -o hello". But without Makefile how make works? How make is gives executable as same name as source?
make has a database of built in rules. These rules include recipes for a number of common operations.
The GNU Make Manual covers (some at least) of these recipes in the Catalogue of Built-Inf Rules section.
Additionally, the output from the -p/--print-data-base option will show you all of the rules/recipes and variables that make has built-in.
the make command of your compiler will, if no further arguments are given and no makefile is present, use default parameters. Default parameters are, in the case of your hello.c (a normal c file) and your compiler settings (presumably fresh from install) to make an executable with the same name as the input file.
Thats just how the compiler is made.
I tried to use a make file in code::blocks but I am doing it wrong. I have the version installed with the compilers included. http://sourceforge.net/projects/codeblocks/files/Binaries/10.05/Windows/codeblocks-10.05mingw-setup.exe/download. What do I do with the make file? It starts with:
CC=gcc
best, US
You don't tend to execute the make file itself, rather you execute make, giving it the make file as an argument:
make -f pax.mk
If your make file is actually one of the standard names (like makefile or Makefile), you don't even need to specify it. It'll be picked up by default (if you have more than one of these standard names in your build directory, you better look up the make man page to see which takes precedence).
As paxdiablo said make -f pax.mk would execute the pax.mk makefile, if you directly execute it by typing ./pax.mk, then you would get syntax error.
Also you can just type make if your file name is makefile/Makefile.
Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
Check out more about makefile at this Tutorial : Basic understanding of Makefile