Think that a MC has an external clock 16MHz and uses internal prescaler #16. It has a embedded code that enables serial at a boudrate of 9600.
What is the boudrate if external clock is changed to 8MHz and internal prescaler to 4.
Explain why.
Can anyone help me about this problem
It depends on the uC code implementation. Guess the baudrate should be the same if your code works.
Related
I am using Waveshare 1.54" ePaper Module. Using SPI peripheral:
CPU freq is 16Mhz
SPI Prescaler DIV by 8
MSB FIRST
CPOL=0, CPHA=1
The Display does not response but it respond with TI CC1310 properly.
The problem with SPI is after transmitting byte it does not go to ideal high state.
I have checked with logic analyser.
The SPI is initialised thus:
/****************** Initializing The SPI Peripheral ******************/
void SPI_setup(void)
{
CLK_PeripheralClockConfig(CLK_PERIPHERAL_SPI, ENABLE); //Enable SPI Peripheral Clock
//Set the MOSI, MISO and SCk at high Level.
//GPIO_ExternalPullUpConfig(GPIOC, (GPIO_Pin_TypeDef)(GPIO_PIN_6),ENABLE);
SPI_DeInit();
SPI_Init(SPI_FIRSTBIT_MSB, //Send MSB First
SPI_BAUDRATEPRESCALER_8, //Fosc/16 = 1MHz
SPI_MODE_MASTER,
SPI_CLOCKPOLARITY_LOW, //IDEAL Clock Polarity is LOW
SPI_CLOCKPHASE_2EDGE, //The first clock transition is the first data capture edge
SPI_DATADIRECTION_2LINES_FULLDUPLEX, //Only TX is Enable
SPI_NSS_SOFT,
0x00);
SPI_Cmd(ENABLE);
}
This is pretty much the same problem you had at Issue in interfacing SPI e-ink display with PIC 18F46K22 only on a different processor. Worth noting that CPHA on STM8 has the opposite sense to CPE on PIC18 which may be the cause of your error. That is to say that CPHA=1 on the STM8 has the same effect as CKE=0 on the PIC18. You really have to look at the timing diagrams for each part carefully.
From https://www.waveshare.com/wiki/1.54inch_e-Paper_Module:
Compare with the STM8 reference manual:
Clearly you need one of:
CPHA=1 / CPOL=1 (SPI_CLOCKPOLARITY_HIGH / SPI_CLOCKPHASE_2EDGE) or
CPHA=0 / CPOL=0 (SPI_CLOCKPOLARITY_LOW / SPI_CLOCKPHASE_1EDGE)
If it is the SCLK that you want to be normally-high, then you need the first option - although I fail to see why that is "ideal", the Waveshare diagram clearly indicates that either is acceptable.
I had configured GPIO PR4 to work as external interrupt trigger on raising edge.but the interrupt ISR not trigger.same code worked well with GPIO PC5.My platform is Cortex M3 (TI F28M36x).
GPIO PC5 has same useage with PR4(different interrupt source)worked well.
I had check the external wave in PR4 (high level more than 3.0V).
I found PR4 use AHP bus,but PC5 use APB bus,I wonder is this difference make the different result?
My configure code like this:
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
GPIOPinTypeGPIOInput(GPIO_PORTR_BASE, GPIO_PIN_4);
GPIOPinIntClear(GPIO_PORTR_BASE,GPIO_PIN_4);
GPIOIntTypeSet(GPIO_PORTR_BASE, GPIO_PIN_4, GPIO_BOTH_EDGES);
IntRegister(INT_GPIOR, IntGPIORHandler);
IntEnable(INT_GPIOR);
GPIOPinIntEnable(GPIO_PORTR_BASE, GPIO_PIN_4);
ISR(IntGPIORHandler) never entered when debug in CCS tools.
I have found solution on TI community.It's not result in AHB problem but driverlib is too old.
https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/552983?tisearch=e2e-sitesearch&keymatch=GPIO%20port%20R%20interrupt
I use these code instead "IntRegister() and IntEnable()".
IntRegister(148, IntGPIORHandler);
HWREG(0xE000E110) = 1 << (132 - 128);
According to the datasheet snippet above, TIM1 can be clocked by the internal clock (CK_INT). What is this internal clock? I have a feeling that it's just the APB1 Timer Clocks (Mhz) in the below clock tree, but is that correct? Why is it called an internal clock in the datasheet?
From the 48MHz limit I'm assuming it's an STM32F0 series MCU.
The clock tree is documented a few chapters back, in Reset and clock control (RCC) / Clocks.
Why is it called an internal clock in the datasheet?
Because it is, well... internal. As opposed to an external clock, which is coming from an external source.
I'm a bit lost with STM32L486 clock management.
I want to change the clock frequency at run-time. Typically I want to be in Low-Power Run/Sleep mode most of the time, and at full frequency the rest of the time.
I know how to set up SysClk either at 80MHz using PLL or at 1MHz using MSI for example.
However the problem is that changing Sysclk is messing up most peripherals setup. For example the USART is not working anymore if I change the clock.
Is it a common practice to do that ( changing the frequency at runtime ) ?
The peripherals I need to use are: LPTIM ( no problem since they can be clocked independantly from SysClk ), ADC, AES accelerator, USART, TIM, SPI.
On STM32L4xx it is not so hard, if you look on "Clock tree" figure in datasheet, many peripherals which are clock dependent (USART, LPTIM, I2C, ..) can be driven with other clock sources than BUS clock, there is also possible to use LSE or internal HSI.
Although internal HSI is not crystal controlled is from my experience enough accurate for UART, also in bigger range of temperatures, but you can tune frequency of this oscillator by comparing its frequency with an external and more accurate clock during runtime, or use auto-buadrate detection.
How can I increase the USART baud rate to 2Mbps, 3Mbps or 4Mbps. I am using STM32L151RCT6A, I am able to run to 921600. I have set clock with PLL 32MHz. On the datasheet it is given, which shows it is possible, Has anyone ever done this?
The datasheet only outlined the specific part and its peripheral set and electrical characteristics. For information on how to use the device you need the Reference Manual. This gives the following equation for baud rate:
Tx/Rx baud = CK_APB1 / (8 x (2 - OVER8) x USARTDIV)
Where USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
When OVER8=0, the fractional part is coded on 4 bits and programmed by the
DIV_fraction[3:0] bits in the USART_BRR register
When OVER8=1, the fractional part is coded on 3 bits and programmed by the
DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction3 must be kept
cleared.
The USARTs are on the APB1 bus, Figure 12 in the reference manual is the clock tree, which shows how the APB1 clock is derived from the PLL clock. The maximum APB1 clock is 32MHz. OVER8=1 is required for higher speeds, giving:
baud = 32X106 / (USARTDIV x 8).
So USARTDIV = 32X106 / (baud x 8)
For 4Mbps therefore, USARTDIV=1 (see table 138 S.No.12 for details). For 2Mps, USARTDIV=2. To achieve 3Mbps you will have to reduce the APB1 clock to 24MHz and set USARTDIV=1 (see table 131). But note that the clock rate changes for all other APB1 peripherals too.
The simplest way to correctly program the USART baud rate is via the STM32L1xx standard peripheral library. Also to determine the correct peripheral clock settings (and more), and generate initialisation code, you can use STM's MicroXplorer tool.