I have been given a makefile which I modified into this:
############################################
# Makefile using OCI (Oracle Call Interface)
# D. LaRue - May, 2001
############################################
ORACLE_HOME=/opt/oratcp11/product/11.2.0/client11R2_32bits
CC=/opt/SUNWspro/SUNWspro12/sparc/SUNWspro/bin/cc
COMMON_SRC=../common
BNS_INCLUDE=../include
LIBHOME=$(ORACLE_HOME)/lib/
RDBMSLIB=$(ORACLE_HOME)/rdbms/lib/
WSSCOMMON_LIB=/vobs/wssCommon/lib_32
TARGET_DIR=.
LLIBCRYPTO =-lbnscrypto
LSOLCRYPTO =-lcryptoutil -lpkcs11
WSSLIBS =-lwssmbx -ldes
LIBRDBMS_CLT =-lclient11 -lvsn11 -lcommon11 -lgeneric11 -lmm
LLIBCLNTSH =-lclntsh -ldl
CORELIBS =-lcore11 -lnls11
LDLIBS =-lnsl -lsocket -lgen -lm
EXSYSLIBS =-R $(ORACLE_HOME)/lib
STATICTTLIBS =$(LLIBRDBMS_CLT) $(CORELIBS) $(WSSLIBS) $(LLIBCRYPTO)
OCISHAREDLIBS =$(LLIBCLNTSH) $(LDLIBS) -Bstatic $(STATICTTLIBS) -Bdynamic $(LSOLCRYPTO)
LDFLAGS =-L$(ORACLE_HOME)/lib -L$(ORACLE_HOME)/rdbms/lib -L$(WSSCOMMON_LIB) -L../lib_32
INCLUDE =-I$(ORACLE_HOME)/rdbms/demo -I$(ORACLE_HOME)/rdbms/public -I$(ORACLE_HOME)/plsql/public -I$(ORACLE_HOME)/network/public -I$(COMMON_SRC) -I$(BNS_INCLUDE) -I.
CFLAGS =$(INCLUDE) $(LDFLAGS) -g -Xt
BESSOBJS=bessToWss.o
COMMONLIST=$(COMMON_SRC)/oracle.c \
$(COMMON_SRC)/logger.c
INTFOBJS=$(BESSOBJS) $(COMMONLIST)
ALL: $(TARGET_DIR)/bessToWss
$(TARGET_DIR)/bessToWss: $(INTFOBJS)
$(CC) $(CFLAGS) $(INTFOBJS) $(OCISHAREDLIBS) -o $#
clean:
$(RM) *.o
When I run the file I get an error
". Stop.e: Error: Don't know how to make "bessToWss
Any idea what is wrong? I run this on some unix machine via a script. The script calls make after sets some paths or some other settings. As you can see I'm not sure how it's called.
Thanks :)
The error message looks peculiar — do you have CRLF line endings in the makefile?
". Stop.e: Error: Don't know how to make "bessToWss
That could be:
/bin/make: Error: Don't know how to make "bessToWssCR". Stop.
where the CR is the carriage return moving the print position back to the start of the line.
Did you create the makefile, or edit it, on a Windows machine? Did you FTP or copy it without using a text mode transfer, so the CRLF line-endings were preserved?
If so, get rid of the carriage returns. Edit the file on Unix with vim and do :set fileformat=unix and save again.
Under this hypothesis, make is trying to build a program whose name includes a CR (carriage return) in the name and you've not given it a rule for doing that.
Related
what i'm doing wrong?
And can you send some helpful links to make my work with makefiles easier and better?
get_next_line.o: file not recognized: File format not recognized
collect2: error: ld returned 1 exit status
Makefile:27: recipe for target 'gnl' failed
make: *** [gnl] Error 1
+++
SRC = gnl.c
OBJ = $(SRC:.c=.o)
INCLUDES = gnl.h
NAME = gnl
CFLAGS = -Wall -Werror -Wextra
CC = gcc
DIR = LIBFT
%.o: %.c $(SRC) $(INCLUDES)
$(CC) $(CFLAGS) -c $<
all: $(NAME)
$(NAME): $(OBJ)
make -C $(DIR)
$(CC) $(CFLAGS) -o $(NAME) $(OBJ) -L. $(DIR)/libft.a
clean:
make clean -C $(DIR)
rm -f $(OBJ)
fclean:
make fclean -C $(DIR)
rm -f $(NAME)
re: fclean all
This is not a make error by itself. It says
get_next_line.o: file not recognized: File format not recognized
so that is your problem. Somehow you managed to have a .o file in your directory that is corrupted. Remove it and things will go better.
You have misunderstood the error message. The error message is referring to the file get_next_line.o, not the makefile.
It is the linker (ld) that is reporting the error not make. The command that has failed is that for the target gnl.
It can even be simpler...
It just happened to me with a Makefile.
In the line (in the Makefile) that creates the executable, where there are different names of objects .o, there was a typo. I left the name of the file .cu (CUDA format) instead of .o.
I ran into this error recently, and I have a couple of suggestions that might help. My problem was not a bad .o file, but rather a 32-bit installation rather than a 64-bit installation. If this is the case for you, too, you might get more complete functionality by trying this solution.
In my case, the makefile(s) in question needed different CFLAGS depending on whether the installation was 64-bit or 32-bit. Here are some lines from the README of the project I was trying to make.
By default, the C/C++ software are compiled in 32 bits with the options (-Os) but can be compiled in 64 bits, -m64 is added to the CFLAGS variable in <certain makefiles in the project are listed>
My suggestion is to first try adding -m64 to your CFLAGS. If that doesn't work, delete the -m64 and replace it with -Os.
That is, first try having the following line:
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -m64
Then, from the command line, run
make clean
Followed by whatever make commands you use for your install.
If that doesn't work, change the line in question to
CFLAGS = -g3 -Wall -Wextra -fPIC -DREPLICATION_ENABLED -DJOURNALING_ENABLED -Os
Then make clean and the other make stuff.
If some of the C objects are 64-bit and some are 32-bit (I don't know if such a situation actually exists), you might have to do something different.
This worked in my case, details of which you can see here.
Please comment to let me know if it works for you.
Introduction: I made a file called temperature 2.c and when I use the terminal to ‘make’ the file, it returns an error: make: *** No rule to make target 'temperature 2'. Stop.
Terminal output screenshot
This is what I type into the terminal window.
make temperature\ 2
Version Information: I'm using macOS 10.12.5 with Apple LLVM version 8.1.0 (clang-802.0.42)Xcode Version 8.3.2 (8E2002)
Additional Information: I've tried using make "temperature 2" as someone suggested that it works on Windows but it's not working on Mac.
I have selected the correct directory in the terminal window and I'm able to compile all other files flawlessly.
Screenshot of the file
I'm aware of the fact that I can simply replace the space with an underscore to fix the issue but I want to know why this is happening in the first place. Terminal works fine handling other directories which have a space in their name (using a backslash), so why isn't it working in this case?Thanks in advance.
Make comes with several built in rules, but they won't be designed to cope with spaces or other "unusual" characters in the file names, so you'll need to write a Makefile that overrides them or change your filenames.
This rule is the one you're using - you have to put quotes around the target file $# and input file $<.
%: %.c
$(CC) $(CFLAGS) -o "$#" "$<"
When calling make, it requires you to have a Makefile, for quick and simple one file c program,
try
gcc -o "temperature 2" "temperature 2.c"
or
clang -o "temperature 2" "temperature 2.c"
Your make clearly tells you that with:
make: *** No rule to make target 'temperature 2'. Stop.
Make feeds the commands to a shell that executes them as commands. If you have one line like this:
.c.o:
$(CC) $(CFLAGS) -c -o $# $<
when you try to do
make "some thing".o
it will try to find a file called "some thing.c" and will execute
cc -c -o some thing.o some thing.c
which is to try to compile to some the three files thing.o, some and thing.c
But if you change the rule to
.c.o:
$(CC) $(CFLAGS) -c -o "$#" "$<"
it will feed the shell with this
cc -c -o "some thing.o" "some thing.c"
that will produce the correct behaviour.
Makefile
.c.o:
$(CC) $(CFLAGS) -c -o "$#" "$<"
Sample run (in a FreeBSD system):
$ make "the problem.o"
cc -O -pipe -c -o "the problem.o" "the problem.c"
Usually if I want to compile a C program called number_input.c I would type
cc -o number_input number_input.c
I want to use my mac terminal to make a script so that I don't have to type that extra word. Originally I did this to save myself 1 sec of programming but ironically I've spent over 2 hrs trying to get this to work.
a= echo "$1" | rev | cut -c3- | rev
echo $a
cc -o $a $1
echo $1
This is my output:
number_input
clang: error: no input files
number_input.c
I can tell that the names are being inputted correctly but for some reason the cc command isn't taking in the value of $1? I am assuming that somehow the $1 isn't directly converted into a string or something like that but I am not sure.
Your error is on the first line, since you're not assigning anything to a:
a=$(echo "$1" | rev | cut -c3- | rev)
Would fix the problem (for well-behaved filenames, at least, since you're missing quotes further down in your script). A space after a means you're assigning an empty string to it and then running the commands in the pipeline.
Instead of going to all the effort of reversing the twice, just remove the last two characters with ${1%??}:
cc -o "${1%??}" "$1"
The most common tool to do this is make. It reads the recipes from a file named Makefile in the directory it is run, and performs any tasks necessary. It is smart enough to check the file timestamps to detect if or which parts of your projects need to be re-compiled. Here is an example Makefile:
CC := gcc
CFLAGS := -Wall -O2
LDFLAGS := -lm
PROGS := number_input
.PHONY: all clean
all: $(PROGS)
clean:
rm -f $(PROGS)
$(PROGS): %: %.c
$(CC) $(CFLAGS) $^ $(LDFLAGS) -o $#
Note that indentation in a Makefile must use tabs, not spaces. If you copy the above, and paste to a file, you will need to run sed -e 's|^ *|\t|' -i Makefile to fix the indentation.
The first three lines name the compiler used, the compiler options, and the linking options. The -lm linking option is not needed for your particular use case; I just included it because you will sooner or later want to use <math.h>, and then you do need to include the -lm linking option.
The PROGS line names your programs. You can specify more than one, just separate them by spaces.
The .PHONY: line tells make that targets all and clean are "phony", that they do not generate files of that name.
The all recipe, as the first recipe in a Makefile, is the default recipe that is followed, when you run make. This one tells that all programs listed in PROGS should be built.
The clean recipe (run make clean) removes all temporary files and compiled files from the directory -- essentially cleaning it.
The last recipe is a tricky one. It says that all the files listed in PROGS are each built from a file having the same name plus a .c suffix. The $^ refers to the .c file name, and $# to the file name without the suffix.
If this Makefile were used for returning exercises via email to a teacher, I'd also add a new .PHONY target, tarball:
CC := gcc
CFLAGS := -Wall -O2
LDFLAGS := -lm
PROGS := number_input
TAR := $(notdir $(CURDIR)).tar
.PHONY: all clean tarball
all: $(PROGS)
clean:
rm -f $(PROGS)
tarball: clean
rm -f ../$(TAR)
tar -cf ../$(TAR) $(notdir $(CURDIR))/
$(PROGS): %: %.c
$(CC) $(CFLAGS) $^ $(LDFLAGS) -o $#
Running make will compile number_input, if number_input.c has been modified after the last time number_input was compiled, or if number_input does not exist yet.
Running make TAR=myname-ex01.tar tarball removes the compiled files from the current directory, then creates a tarball of the current directory (and its subdirectories, if any) in the parent directory as myname-ex01.tar. If you run just make tarball, the tar file name will be the same as the name of the current directory, but with a .tar suffix.
I hope you can see why writing a Makefile is so useful.
I'm having a problem with a C Makefile.
This is the code for the Makefile in bash:
CC=gcc
CFLAGS=-g -Wall
CCLINK=$(CC)
OBJS=flight.o runway.o airport.o main.o
RM=rm -f
# Creating the executable (airport)
airport: $(OBJS)
$(CCLINK) -o airport $(OBJS)
# Creating object files using default rules
main.o: main.c airport.h ex2.h flight.h runway.h
airport.o: airport.c airport.h ex2.h flight.h runway.h
runway.o: runway.c runway.h ex2.h flight.h
flight.o: flight.c flight.h ex2.h
# Cleaning old files before new make
clean:
$(RM) airport *.o *.bak *~ "#"* core
When I make the file, it says that:
make: `airport` is up to date.
After that - I can call "airport" in bash and it lets me enter some inputs the way I want it to be.
BUT- when I'm trying to check if "airport" is compiled by:
gcc -g -Wall -c airport
I get an error says that:
gcc: airport: linker input file unused because linking not done
Does someone know what could be the problem?
Thanks!
Gavriel.
The aim of Makefile is to avoid recompiling a file if its source is unchanged; when it happens, make says that the file is up to date.
This might be annoying if you want to check again the warnings. Then, simply call make to recompile everything, by typing
make clean ; make
Another goal of Makefile is to avoid typing the gcc commands by yourself, prone to errors. For instance, at the end of your question, you ask to make an object file from an executable (option -c), which is wrong. The good way to make an object file is to call make :
make airport.o
Finally, to produce the executable, you can either type
make airport
or, since airport: is the first target, type
make
I was compiling some C code for an assignment and I ran "make codeFile", where "codeFile" was the name of my C program, and even though I didn't have a makefile, an executable was created, and it ran and worked correctly.
Does anyone know why this worked? Why does make compile something even if I don't have a makefile? The only reference I could find was this:
http://daly.axiom-developer.org/TimothyDaly_files/class5/node5.html
Make has an internal database with implicit rules. You can use make -p to list them. Also make -d will tell you which rules are being applied, so that would help you discover which implicit rules are being used in this case.
Make has several pre-defined implicit rules. In particular, in your case, it uses two such rules when trying to determine what to do for the target codeFile:
%: %.o # Link object file
$(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)
%.o: %.c # Compile C source code
$(CC) $(CPPFLAGS) $(CFLAGS) -c
Using the make command without makefiles?
make has implicit rules that work as defaults unless you override them.
According to the make man page:
make -p -f/dev/null
will list all of the implicit rules (and relevant environment variables) without attempting to actually remake files.
To demonstrate the usage, I ran make in Cygwin, which gave me an exe file. Note no .c on the name passed to make:
$ ls
hello.c
$ make hello
cc hello.c -o hello
$ ls
hello.c hello.exe
I also ran this in Ubuntu Linux, and my result was nearly the same as above, but the .exe extension was not there, instead I had the plain hello executable:
$ ls
hello.c hello
Step by step derivation
I believe the relevant pieces of the make implicit rules are as follows:
CC = cc
cc is aliased to CC
LINK.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
a LINK format is created, where the flags will be empty, and the TARGET_ARCH variable is also empty (to allow users to set values for various target architectures.) Then we have:
%: %.c
# recipe to execute (built-in):
$(LINK.c) $^ $(LOADLIBES) $(LDLIBS) -o $#
The ^ variable is the prerequisite, hello.c. The other variables are empty. These are followed by the -o flag and the target name. The empty variables explain the extra spaces in the command make ran:
cc hello.c -o hello
And the %: %.c matched the target given to make with the filename of the same target name ending in .c, which caused the recipe to execute.